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IF Diversity Receiver AD6655
FEATURES
SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at 70 MHz @ 150 MSPS SFDR = 80 dBc to 70 MHz @ 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS output supply Integer 1-to-8 input clock divider Integrated dual-channel ADC Sample rates up to 150 MSPS IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Integrated wideband digital downconverter (DDC) 32-bit complex, numerically controlled oscillator (NCO) Decimating half-band filter and FIR filter Supports real and complex output modes Fast attack/threshold detect bits Composite signal monitor Energy-saving power-down modes
APPLICATIONS
Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 150 MSPS ADC. 2. Integrated wideband decimation filter and 32-bit complex NCO. 3. Fast overrange detect and signal monitor with serial output. 4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz. 5. Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS. 6. SYNC input allows synchronization of multiple devices. 7. 3-bit SPI port for register programming and register readback.
FUNCTIONAL BLOCK DIAGRAM
AVDD FD[0:3]A FD BITS/THRESHOLD DETECT I VIN+A VIN-A SHA ADC Q LP/HP DECIMATING HB FILTER + FIR DVDD DRVDD
AD6655
CMOS/LVDS OUTPUT BUFFER
D13A D0A
VREF SENSE CML RBIAS VIN-B SHA VIN+B ADC I MULTI-CHIP SYNC FD BITS/THRESHOLD DETECT REF SELECT Q LP/HP DECIMATING HB FILTER + FIR SIGNAL MONITOR 32-BIT TUNING NCO
fADC /8
NCO
DIVIDE 1 TO 8 DUTY CYCLE STABILIZER DCO GENERATION
CLK+ CLK- DCOA DCOB
CMOS OUTPUT BUFFER
D13B D0B
PROGRAMMING DATA
SIGNAL MONITOR DATA
SIGNAL MONITOR INTERFACE
SPI
AGND
SYNC
FD[0:3]B
NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06709-001
SMI SMI SMI SDFS SCLK/ SDO/ PDWN OEB
SDIO/ SCLK/ CSB DCS DFS
DRGND
AD6655 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 ADC DC Specifications--AD6655BCPZ-80/ AD6655BCPZ-105......................................................................... 5 ADC DC Specifications--AD6655BCPZ-125/ AD6655BCPZ-150......................................................................... 6 ADC AC Specifications--AD6655BCPZ-80/ AD6655BCPZ-105......................................................................... 7 ADC AC Specifications--AD6655BCPZ-125/ AD6655BCPZ-150......................................................................... 8 Digital Specifications--AD6655BCPZ-80/ AD6655BCPZ-105......................................................................... 9 Digital Specifications--AD6655BCPZ-125/ AD6655BCPZ-150....................................................................... 11 Switching Specifications--AD6655BCPZ-80/ AD6655BCPZ-105....................................................................... 13 Switching Specifications--AD6655BCPZ-125/ AD6655BCPZ-150....................................................................... 14 Timing Specifications ................................................................ 15 Absolute Maximum Ratings.......................................................... 18 Thermal Characteristics ............................................................ 18 ESD Caution................................................................................ 18 Pin Configurations and Function Descriptions ......................... 19 Equivalent Circuits ......................................................................... 23 Typical Performance Characteristics ........................................... 24 Theory of Operation ...................................................................... 29 ADC Architecture ...................................................................... 29 Analog Input Considerations.................................................... 29 Voltage Reference ....................................................................... 31 Clock Input Considerations ...................................................... 32 Power Dissipation and Standby Mode..................................... 34 Digital Outputs ........................................................................... 35 Digital Downconverter .................................................................. 37 Downconverter Modes .............................................................. 37 Numerically Controlled Oscillator (NCO) ............................. 37 Half-Band Decimating Filter and FIR Filter........................... 37 fADC/8 Fixed-Frequency NCO ................................................... 37 Numerically Controlled Oscillator (NCO) ................................. 38 Frequency Translation ............................................................... 38 NCO Synchronization ............................................................... 38 Phase Offset................................................................................. 38 NCO Amplitude and Phase Dither.......................................... 38 Decimating Half-Band Filter and FIR filter................................ 39 Half-Band Filter Coefficients.................................................... 39 Half-Band Filter Features .......................................................... 39 Fixed-Coefficient FIR Filter...................................................... 39 Synchronization.......................................................................... 40 Combined Filter Performance.................................................. 40 Final NCO ................................................................................... 40 ADC Overrange and Gain Control.............................................. 41 Fast Detect Overview................................................................. 41 ADC Fast Magnitude ................................................................. 41 ADC Overrange (OR)................................................................ 42 Gain Switching............................................................................ 42 Signal Monitor ................................................................................ 44 Peak Detector Mode................................................................... 44 RMS/MS Magnitude Mode....................................................... 44 Threshold Crossing Mode......................................................... 45 Additional Control Bits ............................................................. 45 DC Correction ............................................................................ 45 Signal Monitor SPORT Output ................................................ 46 Channel/Chip Synchronization.................................................... 47 Serial Port Interface (SPI).............................................................. 48 Configuration Using the SPI..................................................... 48 Hardware Interface..................................................................... 48 Configuration Without the SPI ................................................ 49 SPI Accessible Features.............................................................. 49 Memory Map .................................................................................. 50 Reading the Memory Map Register Table............................... 50 Memory Map Register Table..................................................... 51 Memory Map Register Description ......................................... 55 Applications Information .............................................................. 59 Design Guidelines ...................................................................... 59 Evaluation Board ............................................................................ 61 Power Supplies ............................................................................ 61
Rev. 0 | Page 2 of 84
AD6655
Input Signals ................................................................................61 Output Signals .............................................................................61 Default Operation and Jumper Selection Settings..................62 Alternative Clock Configurations.............................................62 Alternative Analog Input Drive Configuration ......................63 Schematics....................................................................................64 Evaluation Board Layouts ..........................................................74 Bill of Materials ...........................................................................82 Outline Dimensions........................................................................84 Ordering Guide ...........................................................................84
REVISION HISTORY
11/07--Revision 0: Initial Version
Rev. 0 | Page 3 of 84
AD6655 GENERAL DESCRIPTION
The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a halfband decimating filter, a fixed FIR filter, and an fADC/8 fixedfrequency NCO. In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. After digital processing, data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A. The AD6655 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of -40C to +85C.
Rev. 0 | Page 4 of 84
AD6655 SPECIFICATIONS
ADC DC SPECIFICATIONS--AD6655BCPZ-80/AD6655BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = -1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 1 VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD (CMOS Mode) DRVDD (LVDS Mode) Supply Current IAVDD 2, 3 IDVDD2, 3 IDRVDD2 (3.3 V CMOS) IDRVDD2 (1.8 V CMOS) IDRVDD2 (1.8 V LVDS) POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power
1 2
Temperature Full Full Full Full 25C 25C Full Full Full Full 25C Full Full Full
Min 14
AD6655BCPZ-80 Typ Max
Min 14
AD6655BCPZ-105 Typ Max
Unit Bits
-3.6
Guaranteed 0.2 0.6 -1.8 -0.1 0.2 0.2 15 95 5 7 0.85 2 8 6 18 0.6 0.75
-4.3
Guaranteed 0.2 0.6 -2.2 -0.5 0.2 0.2 15 95 5 7 0.85 2 8 6 18 0.6 0.75
% FSR % FSR % FSR % FSR ppm/C ppm/C mV mV LSB rms V p-p pF k
Full Full Full Full Full Full Full Full Full Full Full Full Full
1.7 1.7 1.7
1.8 3.3 1.8 235 175 18 8 55 470 755 800 52 2.5
1.9 3.6 1.9 420
1.7 1.7 1.7
1.8 3.3 1.8 315 225 21 11 56 620 995 1040 68 2.5
1.9 3.6 1.9 575
V V V mA mA mA mA mA mW mW mW mW mW
490
650
8
8
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure. Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately 5 pF loading on each output bit. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 5 of 84
AD6655
ADC DC SPECIFICATIONS--AD6655BCPZ-125/AD6655BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = -1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 1 VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD (CMOS Mode) DRVDD (LVDS Mode) Supply Current IAVDD 2, 3 IDVDD2, 3 IDRVDD2 (3.3 V CMOS) IDRVDD2 (1.8 V CMOS) IDRVDD2 (1.8 V LVDS) POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-down Power
1 2
Temperature Full Full Full Full 25C 25C Full Full Full Full 25C Full Full Full
Min 14
AD6655BCPZ-125 Typ Max
Min 14
AD6655BCPZ-150 Typ Max
Unit Bits
-4.7
Guaranteed 0.3 0.6 -2.7 -0.8 0.3 0.1 15 95 5 7 0.85 2 8 6 18 0.7 0.7
-5.1
Guaranteed 0.2 0.6 -3.2 -1.0 0.2 0.2 15 95 5 7 0.85 2 8 6 18 0.7 0.8
% FSR % FSR % FSR % FSR ppm/C ppm/C mV mV LSB rms V p-p pF k
Full Full Full Full Full Full Full Full Full Full Full Full Full
1.7 1.7 1.7
1.8 1.8 1.8 390 270 26 13 57 770 1215 1275 77 2.5
1.9 3.6 1.9 705
1.7 1.7 1.7
1.8 1.8 1.8 440 320 28 17 57 870 1395 1450 77 2.5
1.9 3.6 1.9 805
V V V mA mA mA mA mA mW mW mW mW mW
810
920
8
8
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure. Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately 5 pF loading on each output bit. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 6 of 84
AD6655
ADC AC SPECIFICATIONS--AD6655BCPZ-80/AD6655BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = -1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 3.
Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR 2 fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz TWO-TONE SFDR fIN = 29.12 MHz, 32.12 MHz (-7 dBFS) fIN = 169.12 MHz, 172.12 MHz (-7 dBFS) CROSSTALK 3 ANALOG INPUT BANDWIDTH
1 2
Temperature 25C 25C Full 25C 25C 25C 25C Full 25C 25C
Min
AD6655BCPZ-80 Typ Max 74.9 74.8
Min
AD6655BCPZ-105 Typ Max 74.8 74.7
Unit dB dB dB dB dB dBc dBc dBc dBc dBc
73.0 74.5 73.4 -86 -85 -74 -84 -83
73.0 74.3 73.4 -86 -85 -74 -84 -83
25C 25C Full 25C 25C 25C 25C Full 25C 25C 25C 25C Full 25C
86 85 74 84 83 -93 -90 -82 -89 -86 85 81 95 650 74
86 85 84 83 -93 -90 -82 -89 -86 85 81 95 650
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB MHz
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. See the Applications Information section for more information about the worst other specifications for the AD6655. 3 Crosstalk is measured at 100 MHz with -1 dBFS on one channel and with no input on the alternate channel.
Rev. 0 | Page 7 of 84
AD6655
ADC AC SPECIFICATIONS--AD6655BCPZ-125/AD6655BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = -1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted. Table 4.
Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR 2 fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz TWO-TONE SFDR fIN = 29.12 MHz, 32.12 MHz (-7 dBFS) fIN = 169.12 MHz, 172.12 MHz (-7 dBFS) CROSSTALK 3 ANALOG INPUT BANDWIDTH
1 2 3
Temperature 25C 25C Full 25C 25C 25C 25C Full 25C 25C 25C 25C Full 25C 25C 25C 25C Full 25C 25C 25C 25C Full 25C
Min
AD6655BCPZ-125 Typ Max 74.7 74.6
AD6655BCPZ-150 Min Typ Max 74.6 74.5 72.5 73.9 73.0 -85 -84
Unit dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB MHz
73.0 74.2 73.3 -86 -85 -73 -84 -83 86 85 73 84 83 -92 -90 -82 -88 -84 85 81 95 650
-73 -83 -77 85 80 73 76 74 -87 -80 -80 -76 -74 85 81 95 650
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. See the Applications Information section for more information about the worst other specifications for the AD6655. Crosstalk is measured at 100 MHz with -1 dBFS on one channel and with no input on the alternate channel.
Rev. 0 | Page 8 of 84
AD6655
DIGITAL SPECIFICATIONS--AD6655BCPZ-80/AD6655BCPZ-105
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = -1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 5.
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK-) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance Temp Min AD6655BCPZ-80 Typ Max Min AD6655BCPZ-105 Typ Max Unit
Full Full Full Full Full Full Full Full Full Full
CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD + 1.6 AVDD - 0.3 1.1 AVDD 1.2 3.6 0 0.8 -10 +10 -10 +10 4 8 10 12 CMOS 1.2 AVDD - 0.3 1.2 0 -10 -10 8 1.22 0 -10 40 26 2 1.22 0 -92 -10 26 2 1.22 0 -10 38 26 5 3.6 0.6 +10 128 3.6 0.6 -135 +10 4 10 AVDD + 1.6 3.6 0.8 +10 +10 12 3.6 0.6 +10 132
CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD - 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 -10 +10 -10 +10 4 8 10 12 CMOS 1.2 AVDD - 0.3 1.2 0 -10 -10 8 1.22 0 -10 40 26 2 1.22 0 -92 -10 26 2 1.22 0 -10 38 26 5 3.6 0.6 +10 128 3.6 0.6 -135 +10 4 10 AVDD + 1.6 3.6 0.8 +10 +10 12 3.6 0.6 +10 132
V V p-p V V V V A A pF k
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
V V V V A A pF k V V A A k pF V V A A k pF V V A A k pF
Rev. 0 | Page 9 of 84
AD6655
Parameter LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode--DRVDD = 3.3 V High Level Output Voltage IOH = 50 A IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 A CMOS Mode--DRVDD = 1.8 V High Level Output Voltage IOH = 50 A IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 A LVDS Mode, DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode
1 2
Temp
Min
AD6655BCPZ-80 Typ Max
Min
AD6655BCPZ-105 Typ Max
Unit
Full Full Full Full Full Full
1.22 0 -90 -10 26 5
3.6 0.6 -134 +10
1.22 0 -90 -10 26 5
3.6 0.6 -134 +10
V V A A k pF
Full Full Full Full
3.29 3.25 0.2 0.05
3.29 3.25 0.2 0.05
V V V V
Full Full Full Full Full Full Full Full
1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35
1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35
V V V V mV V mV V
Pull up. Pull down.
Rev. 0 | Page 10 of 84
AD6655
DIGITAL SPECIFICATIONS--AD6655BCPZ-125/AD6655BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = -1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 6.
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK-) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance Temp Min AD6655BCPZ-125 Typ Max Min AD6655BCPZ-150 Typ Max Unit
Full Full Full Full Full Full Full Full Full Full
CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD - 0.3 AVDD + 1.6 1.1 V AVDD 1.2 3.6 0 0.8 -10 +10 -10 +10 4 8 10 12 CMOS 1.2 AVDD - 0.3 1.2 0 -10 -10 8 1.22 0 -10 40 26 2 1.22 0 -92 -10 26 2 1.22 0 -10 38 26 5 3.6 0.6 +10 128 3.6 0.6 -135 +10 4 10 AVDD + 1.6 3.6 0.8 +10 +10 12 3.6 0.6 +10 132
CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD - 0.3 AVDD + 1.6 1.1 V AVDD 1.2 3.6 0 0.8 -10 +10 -10 +10 4 8 10 12 CMOS 1.2 AVDD - 0.3 1.2 0 -10 -10 8 1.22 0 -10 40 26 2 1.22 0 -92 -10 26 2 1.22 0 -10 38 26 5 3.6 0.6 +10 128 3.6 0.6 -135 +10 4 10 AVDD + 1.6 3.6 0.8 +10 +10 12 3.6 0.6 +10 132
V V p-p V V V V A A pF k
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
V V V V A A pF k V V A A k pF V V A A k pF V V A A k pF
Rev. 0 | Page 11 of 84
AD6655
Parameter LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode--DRVDD = 3.3 V High Level Output Voltage IOH = 50 A IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 A CMOS Mode--DRVDD = 1.8 V High Level Output Voltage IOH = 50 A IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 A LVDS Mode--DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode
1 2
Temp
Min
AD6655BCPZ-125 Typ Max
Min
AD6655BCPZ-150 Typ Max
Unit
Full Full Full Full Full Full
1.22 0 -90 -10 26 5
3.6 0.6 -134 +10
1.22 0 -90 -10 26 5
3.6 0.6 -134 +10
V V A A k pF
Full Full Full Full
3.29 3.25 0.2 0.05
3.29 3.25 0.2 0.05
V V V V
Full Full Full Full Full Full Full Full
1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35
1.79 1.75 0.2 0.05 250 1.15 150 1.15 350 1.25 200 1.25 450 1.35 280 1.35
V V V V mV V mV V
Pull up. Pull down.
Rev. 0 | Page 12 of 84
AD6655
SWITCHING SPECIFICATIONS--AD6655BCPZ-80/AD6655BCPZ-105
Table 7.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK Period--Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCLKH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode DCS Disabled Divide-by-2 Mode, DCS Enabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode--DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Noninterleaved Mode--DRVDD = 3.3 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved and IQ Mode--DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved and IQ Mode--DRVDD = 3.3 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) LVDS Mode--DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled Pipeline Delay (Latency) NCO Enabled, FIR and fS/8 Mix Disabled (Complex Output Mode) Pipeline Delay (Latency) NCO, FIR, and fS/8 Mix Enabled Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME
1 2
Temp Full Full Full Full Full Full Full Full
AD6655BCPZ-80 Min Typ Max 625 20 10 12.5 3.75 5.63 1.6 0.8 6.25 6.25 80 80
AD6655BCPZ-105 Min Typ Max 625 20 10 9.5 2.85 4.28 1.6 0.8 4.75 4.75 105 105
Unit MHz MSPS MSPS ns ns ns ns ns
8.75 6.88
6.65 5.23
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
1.6 4.0
3.9 5.4 14.0 11.0 4.1 5.8 14.2 10.8 3.9 4.8 7.15 5.35 4.1 5.2 7.35 5.15 4.8 5.3 38 38 109 1.0 0.1 350 2
6.2 7.3
1.6 4.0
3.9 5.4 11.0 8.0 4.1 5.8 11.2 7.8 3.9 4.8 5.65 3.85 4.1 5.2 5.85 3.65 4.8 5.3 38 38 109 1.0 0.1 350 2
6.2 7.3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles Cycles Cycles ns ps rms us Cycles
1.9 4.4
6.4 7.7
1.9 4.4
6.4 7.7
1.6 3.4
6.2 6.7
1.6 3.4
6.2 6.7
1.9 3.8
6.4 7.1
1.9 3.8
6.4 7.1
2.5 3.7
7.0 7.3
2.5 3.7
7.0 7.3
Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors.
Rev. 0 | Page 13 of 84
AD6655
SWITCHING SPECIFICATIONS--AD6655BCPZ-125/AD6655BCPZ-150
Table 8.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK Period--Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCLKH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode, DCS Enabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Noninterleaved Mode--DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Noninterleaved Mode--DRVDD = 3.3 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved and IQ Mode--DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Interleaved and IQ Mode--DRVDD = 3.3 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) LVDS Mode--DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled Pipeline Delay (Latency) NCO Enabled; FIR and fS/8 Mix Disabled (Complex Output Mode) Pipeline Delay (Latency) NCO, FIR, and fS/8 Mix Enabled Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME
1 2
Temp Full Full Full Full Full Full Full Full
AD6655BCPZ-125 Min Typ Max 625 20 10 8 2.4 3.6 1.6 0.8 4 4 125 125
AD6655BCPZ-150 Min Typ Max 625 20 10 6.66 2.0 3.0 1.6 0.8 3.33 3.33 150 150
Unit MHz MSPS MSPS ns ns ns ns ns
5.6 4.4
4.66 3.66
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
1.6 4.0
3.9 5.4 9.5 6.5 4.1 5.8 9.7 6.3 3.9 4.8 4.9 3.1 4.1 5.2 5.1 2.9 4.8 5.3 38 38 109 1.0 0.1 350 3
6.2 7.3
1.6 4.0
3.9 5.4 8.16 5.16 4.1 5.8 8.36 4.96 3.9 4.8 4.23 2.43 4.1 5.2 4.43 2.23 4.8 5.3 38 38 109 1.0 0.1 350 3
6.2 7.3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cycles Cycles Cycles ns ps rms us Cycles
1.9 4.4
6.4 7.7
1.9 4.4
6.4 7.7
1.6 3.4
6.2 6.7
1.6 3.4
6.2 6.7
1.9 3.8
6.4 7.1
1.9 3.8
6.4 7.1
2.5 3.7
7.0 7.3
2.5 3.7
7.0 7.3
Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors.
Rev. 0 | Page 14 of 84
AD6655
TIMING SPECIFICATIONS
Table 9.
Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO SPORT TIMING REQUIREMENTS tCSSCLK tSSLKSDO tSSCLKSDFS Conditions SYNC to the rising edge of CLK setup time SYNC to the rising edge of CLK hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge Delay from rising edge of CLK+ to rising edge of SMI SCLK Delay from rising edge of SMI SCLK to SMI SDO Delay from rising edge of SMI SCLK to SMI SDFS 2 2 40 2 2 10 10 10 10 Min Typ 0.24 0.4 Max Unit ns ns ns ns ns ns ns ns ns ns ns
3.2 -0.4 -0.4
4.5 0 0
6.2 +0.4 +0.4
ns ns ns
Timing Diagrams
CLK+
tPD
DECIMATED CMOS DATA CHANNEL A/B DATA BITS
tDCO
CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS
DECIMATED FD DATA
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
tS tH
06709-109
DECIMATED DCOA/DCOB
Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
CLK+
tPD
tDCO
DECIMATED CMOS DATA
CHANNEL A/B DATA BITS
CHANNEL A/B DATA BITS
CHANNEL A/B DATA BITS
DECIMATED FD DATA
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
CHANNEL A/B FD BITS
tS
DECIMATED DCOA/DCOB
tH
Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
Rev. 0 | Page 15 of 84
06709-012
AD6655
CLK+
tPD
DECIMATED INTERLEAVED CMOS DATA DECIMATED INTERLEAVED FD DATA DECIMATED DCO CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA
tDCO
CHANNEL A: DATA CHANNEL B: DATA
CHANNEL A: FD BITS
CHANNEL B: FD BITS
CHANNEL A: FD BITS
CHANNEL B: FD BITS
CHANNEL A: FD BITS
CHANNEL B: FD BITS
tS tH
06709-013
Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing
CLK+
tPD
DECIMATED CMOS IQ OUTPUT DATA CMOS FD DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA CHANNEL A/B: Q DATA
tDCO
CHANNEL A/B: I DATA CHANNEL A/B: Q DATA CHANNEL A/B: I DATA
CHANNEL A/B: FD BITS
CHANNEL A/B: FD BITS
CHANNEL A/B: FD BITS
CHANNEL A/B: FD BITS
CHANNEL A/B: FD BITS
CHANNEL A/B: FD BITS
tS
DECIMATED DCOA/DCOB
tH
Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing
CLK- CLK+
tPD
LVDS DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA CHANNEL B: DATA CHANNEL A: DATA
LVDS FAST DET DCO- DCO+
CHANNEL A: FD
CHANNEL B: FD
CHANNEL A: FD
CHANNEL B: FD
CHANNEL A: FD
tDCO
06709-015
Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing
CLK+
tSSYNC
SYNC
tHSYNC
06709-016
Figure 7. SYNC Timing Inputs
Rev. 0 | Page 16 of 84
06709-014
AD6655
CLK+ CLK-
tCSSCLK
SMI SCLK
tSSCLKSDFS
SMI SDFS
tSSCLKSDFS
SMI SDO
DATA
DATA
Figure 8. Signal Monitor SPORT Output Timing
Rev. 0 | Page 17 of 84
06709-017
AD6655 ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND VIN+A/VIN+B, VIN-A/VIN-B to AGND CLK+, CLK- to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND SDIO/DCS to DRGND SMI SDO/OEB to DRGND SMI SCLK/PDWN to DRGND SMI SDFS to DRGND D0A/D0B through D13A/D13B to DRGND FD0A/FD0B through FD3A/FD3B to DRGND DCOA/DCOB to DRGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.2 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -40C to +85C 150C -65C to +125C
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 11. Thermal Resistance
Package Type 64-Lead LFCSP 9 mm x 9 mm (CP-64-3)
1 2
Airflow Velocity (m/s) 0 1.0 2.0
JA1, 2 18.8 16.5 15.8
JC1, 3 0.6
JB1, 4 6.0
Unit C/W C/W C/W
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).
Typical JA is specified for a 4-layer PCB with solid ground plane. As shown, airflow increases heat dissipation, which reduces JA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the JA.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 18 of 84
AD6655 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1 INDICATOR
DRGND D5B D4B D3B D2B D1B D0B (LSB) DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK- CLK+
DRVDD D6B D7B D8B D9B D10B D11B D12B D13B (MSB) DCOB DCOA D0A (LSB) D1A D2A D3A D4A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)
AD6655
PARALLEL CMOS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN-B RBIAS CML SENSE VREF VIN-A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB
D5A D6A D7A DRGND DRVDD D8A D9A DVDD D10A D11A D12A D13A (MSB) FD0A FD1A FD2A FD3A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 12. Pin Function Descriptions (Parallel CMOS Mode)
Pin No. Mnemonic ADC Power Supplies 20, 64 DRGND 1, 21 DRVDD 24, 57 DVDD 36, 45, 46 AVDD 0 AGND ADC Analog 37 VIN+A 38 VIN-A 44 VIN+B 43 VIN-B 39 VREF 40 SENSE 42 RBIAS 41 CML 49 CLK+ 50 CLK- ADC Fast Detect Outputs 29 FD0A 30 FD1A 31 FD2A 32 FD3A 53 FD0B 54 FD1B 55 FD2B 56 FD3B Digital Input 52 SYNC Type Ground Supply Supply Supply Ground Input Input Input Input Input/Output Input Input/Output Output Input Input Output Output Output Output Output Output Output Output Input Description Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Digital Power Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (-) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (-) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. (See Table 15 for details.) External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input--True. ADC Clock Input--Complement. Channel A Fast Detect Indicator. (See Table 21 for details.) Channel A Fast Detect Indicator. (See Table 21 for details.) Channel A Fast Detect Indicator. (See Table 21 for details.) Channel A Fast Detect Indicator. (See Table 21 for details.) Channel B Fast Detect Indicator. (See Table 21 for details.) Channel B Fast Detect Indicator. (See Table 21 for details.) Channel B Fast Detect Indicator. (See Table 21 for details.) Channel B Fast Detect Indicator. (See Table 21 for details.) Digital Synchronization Pin. Slave mode only.
Rev. 0 | Page 19 of 84
06709-002
AD6655
Pin No. Mnemonic Digital Outputs 12 D0A (LSB) 13 D1A 14 D2A 15 D3A 16 D4A 17 D5A 18 D6A 19 D7A 22 D8A 23 D9A 25 D10A 26 D11A 27 D12A 28 D13A (MSB) 58 D0B (LSB) 59 D1B 60 D2B 61 D3B 62 D4B 63 D5B 2 D6B 3 D7B 4 D8B 5 D9B 6 D10B 7 D11B 8 D12B 9 D13B (MSB) 11 DCOA 10 DCOB SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Port 33 SMI SDO/OEB 35 34 SMI SDFS SMI SCLK/PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Output Input/Output Description Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel A Data Clock Output. Channel B Data Clock Output. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select. Active low. Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External Pin Mode.
Rev. 0 | Page 20 of 84
AD6655
DRGND D0+ (LSB) D0- (LSB) FD3+ FD3- FD2+ FD2- DVDD FD1+ FD1- FD0+ FD0- SYNC CSB CLK- CLK+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1 INDICATOR
DRVDD D1- D1+ D2- D2+ D3- D3+ D4- D4+ DCO- DCO+ D5- D5+ D6- D6+ D7-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)
AD6655
PARALLEL LVDS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN-B RBIAS CML SENSE VREF VIN-A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB
D7+ D8- D8+ DRGND DRVDD D9- D9+ DVDD D10- D10+ D11- D11+ D12- D12+ D13- (MSB) D13+ (MSB)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 13. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No. Mnemonic ADC Power Supplies 20, 64 DRGND 1, 21 DRVDD 24, 57 DVDD 36, 45, 46 AVDD 0 AGND ADC Analog 37 VIN+A 38 VIN-A 44 VIN+B 43 VIN-B 39 VREF 40 SENSE 42 RBIAS 41 CML 49 CLK+ 50 CLK- ADC Fast Detect Outputs 54 FD0+ 53 FD056 55 59 58 61 60 FD1+ FD1- FD2+ FD2- FD3+ FD3- Type Ground Supply Supply Supply Ground Input Input Input Input Input/Output Input Input/Output Output Input Input Output Output Output Output Output Output Output Output Description Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Digital Power Supply (1.8 V Nominal.) Analog Power Supply (1.8 V Nominal.) Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (-) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (-) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 15 for details. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input--True. ADC Clock Input--Complement. Channel A/Channel B LVDS Fast Detect Indicator 0--True. See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 0--Complement. See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 1--True. See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 1--Complement. See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 2--True See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 2--Complement. See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 3--True. See Table 21 for details. Channel A/Channel B LVDS Fast Detect Indicator 3--Complement. See Table 21 for details.
Rev. 0 | Page 21 of 84
06709-003
AD6655
Pin No. Mnemonic Digital Input 52 SYNC Digital Outputs 63 D0+ (LSB) 62 D0- (LSB) 3 D1+ 2 D1- 5 D2+ 4 D2- 7 D3+ 6 D3- 9 D4+ 8 D4- 13 D5+ 12 D5- 15 D6+ 14 D6- 17 D7+ 16 D7- 19 D8+ 18 D8- 23 D9+ 22 D9- 26 D10+ 25 D10- 28 D11+ 27 D11- 30 D12+ 29 D12- 32 D13+ (MSB) 31 D13- (MSB) 11 DCO+ 10 DCO- SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Port 33 SMI SDO/OEB 35 34 SMI SDFS SMI SCLK/PDWN Type Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input/Output Output Input/Output Description Digital Synchronization Pin. Slave mode only. Channel A/Channel B LVDS Output Data 0--True. Channel A/Channel B LVDS Output Data 0--Complement. Channel A/Channel B LVDS Output Data 1--True. Channel A/Channel B LVDS Output Data 1--Complement. Channel A/Channel B LVDS Output Data 2--True. Channel A/Channel B LVDS Output Data 2--Complement. Channel A/Channel B LVDS Output Data 3--True. Channel A/Channel B LVDS Output Data 3--Complement. Channel A/Channel B LVDS Output Data 4--True. Channel A/Channel B LVDS Output Data 4--Complement. Channel A/Channel B LVDS Output Data 5--True. Channel A/Channel B LVDS Output Data 5--Complement. Channel A/Channel B LVDS Output Data 6--True. Channel A/Channel B LVDS Output Data 6--Complement. Channel A/Channel B LVDS Output Data 7--True. Channel A/Channel B LVDS Output Data 7--Complement. Channel A/Channel B LVDS Output Data 8--True. Channel A/Channel B LVDS Output Data 8--Complement. Channel A/Channel B LVDS Output Data 9--True. Channel A/Channel B LVDS Output Data 9--Complement. Channel A/Channel B LVDS Output Data 10--True. Channel A/Channel B LVDS Output Data 10--Complement. Channel A/Channel B LVDS Output Data 11--True. Channel A/Channel B LVDS Output Data 11--Complement. Channel A/Channel B LVDS Output Data 12--True. Channel A/Channel B LVDS Output Data 12--Complement. Channel A/Channel B LVDS Output Data 13--True. Channel A/Channel B LVDS Output Data 13--Complement. Channel A/Channel B LVDS Data Clock Output--True. Channel A/Channel B LVDS Data Clock Output--Complement. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. SPI Chip Select (Active Low). Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External Pin Mode
Rev. 0 | Page 22 of 84
AD6655 EQUIVALENT CIRCUITS
VIN
SCLK/DFS
1k 26k
06709-004
Figure 11. Equivalent Analog Input Circuit
AVDD
Figure 15. Equivalent SCLK/DFS Input Circuit
1.2V CLK+ 10k 10k CLK-
SENSE
1k
06709-005
Figure 12. Equivalent Clock lnput Circuit
DRVDD
Figure 16. Equivalent SENSE Circuit
AVDD 26k CSB 1k
06709-006
DRGND
Figure 13. Equivalent Digital Output Circuit
Figure 17. Equivalent CSB Input Circuit
AVDD
DRVDD DRVDD 26k 1k SDIO/DCS
06709-007
06709-011
VREF 6k
Figure 14. Equivalent SDIO/DCS Circuit or SMI SDFS Circuit
Figure 18. Equivalent VREF Circuit
.
Rev. 0 | Page 23 of 84
06709-010
06709-009
06709-008
AD6655 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = -1.0 dBFS, 64k sample, TA = 25C, NCO enabled, FIR filter enabled, unless otherwise noted. In the FFT plots that follow, the location of the second and third harmonics is noted when they fall in the pass band of the filter.
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 2.4MHz @ -1dBFS SNR = 74.7dBc (75.7dBFS) SFDR = 86.5dBc fNCO = 18.75MHz
AMPLITUDE (dBFS)
0 -20 -40 -60
150MSPS 140.1MHz @ -1dBFS SNR = 73.7dBc (74.7dBFS) SFDR = 82.8dBc fNCO = 126MHz
AMPLITUDE (dBFS)
SECOND HARMONIC THIRD HARMONIC
THIRD HARMONIC -80 -100 -120 -140 0 5 10 15
SECOND HARMONIC
06709-018
20
25
30
35
FREQUENCY (MHz)
Figure 19. AD6655-150 Single-Tone FFT with fIN = 2.4 MHz, fNCO = 18.75 MHz
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz)
Figure 22. AD6655-150 Single-Tone FFT with fIN = 140.1 MHz, fNCO = 126 MHz
0 -20 -40 -60 THIRD HARMONIC -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 220.1MHz @ -1dBFS SNR = 71.8dBc (72.8dBFS) SFDR = 81.4dBc fNCO = 205MHz
150MSPS 30.3MHz @ -1dBFS SNR = 74.8dBc (75.8dBFS) SFDR = 100dBc fNCO = 24MHz
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
06709-019
Figure 20. AD6655-150 Single-Tone FFT with fIN = 30.3 MHz, fNCO = 24 MHz
0 -20 -40 -60 THIRD HARMONIC -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz)
Figure 23. AD6655-150 Single-Tone FFT with fIN = 220.1 MHz, fNCO = 205 MHz
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 332.1MHz @ -1dBFS SNR = 71.7dBc (72.7dBFS) SFDR = 95.0dBc fNCO = 321.5MHz
150MSPS 140.1MHz @ -1dBFS SNR = 74.3dBc (75.3dBFS) SFDR = 83.3dBc fNCO = 56MHz
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
06709-020
Figure 21. AD6655-150 Single-Tone FFT with fIN = 70.1 MHz, fNCO = 56 MHz
Figure 24. AD6655-150 Single-Tone FFT with fIN = 332.1 MHz, fNCO = 321.5 MHz
Rev. 0 | Page 24 of 84
06709-023
06709-022
06709-021
AD6655
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 445.1MHz @ -1dBFS SNR = 67.4dBc (65.4dBFS) SFDR = 74.1dBc fNCO = 429MHz SECOND HARMONIC THIRD HARMONIC
AMPLITUDE (dBFS)
0 -20 -40 -60
125MSPS 70.3MHz @ -1dBFS SNR = 74.6dBc (75.6dBFS) SFDR = 86.1dBc fNCO = 78MHz
AMPLITUDE (dBFS)
THIRD HARMONIC -80 -100 -120 -140 0 5 10 15 20 25 30 FREQUENCY (MHz)
06709-024
Figure 25. AD6655-150 Single-Tone FFT with fIN = 445.1 MHz, fNCO = 429 MHz
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 FREQUENCY (MHz)
Figure 28. AD6655-125 Single-Tone FFT with fIN = 70.3 MHz, fNCO = 78 MHz
0 -20 -40 -60 THIRD HARMONIC -80 -100 -120 -140 0 5 10 15 20 25 30 FREQUENCY (MHz)
125MSPS 2.4MHz @ -1dBFS SNR = 74.5dBc (75.5dBFS) SFDR = 87.8dBc fNCO = 15.75MHz
AMPLITUDE (dBFS)
125MSPS 140.1MHz @ -1dBFS SNR = 74.1dBc (75.1dBFS) SFDR = 90.3dBc fNCO = 142MHz
AMPLITUDE (dBFS)
SECOND HARMONIC THIRD HARMONIC
06709-025
Figure 26. AD6655-125 Single-Tone FFT with fIN =2.4 MHz, fNCO = 15.75 MHz
0 -20 -40 -60 THIRD HARMONIC -80 -100 -120 -140 0 5 10 15 20 25 30 FREQUENCY (MHz) 125MSPS 30.3MHz @ -1dBFS SNR = 74.7dBc (75.7dBFS) SFDR = 89.6dBc fNCO = 21MHz
Figure 29. AD6655-125 Single-Tone FFT with fIN = 140.1 MHz, fNCO = 142 MHz
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 FREQUENCY (MHz) 125MSPS 220.1MHz @ -1dBFS SNR = 73.4dBc (74.4dBFS) SFDR = 90.2dBc fNCO = 231MHz
AMPLITUDE (dBFS)
06709-026
AMPLITUDE (dBFS)
Figure 27. AD6655-125 Single-Tone FFT with fIN = 30.3 MHz, fNCO = 21 MHz
Figure 30. AD6655-125 Single-Tone FFT with fIN = 220.1 MHz, fNCO = 231 MHz
Rev. 0 | Page 25 of 84
06709-029
06709-028
06709-027
AD6655
120 95 90 85
SNR/SFDR (dBc)
100
SNR/SFDR (dBc AND dBFS)
SFDR (dBFS) SNR (dBFS)
SFDR = +85C SFDR = +25C SFDR = -40C
80
80 75 70 65
60
40 SFDR (dBc) 20 SNR (dBc)
06709-030
85dB REFERENCE LINE
SNR = +25C SNR = +85C SNR = -40C
-80
-70
-60
-50
-40
-30
-20
-10
0
0
50
100
150
200
250
300
350
400
450
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 31. AD6655-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.4 MHz, fNCO = 18.75 MHz
120 SFDR (dBFS) 100
SNR/SFDR (dBc AND dBFS)
Figure 34. AD6655-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with DRVDD = 3.3 V
-1.5 0.5
-2.0
GAIN ERROR (%FSR)
0.4
OFFSET ERROR (%FSR)
06709-035 06709-034
80
SNR (dBFS)
-2.5 OFFSET -3.0 GAIN -3.5
0.3
60 SFDR (dBc) 40 85dB REFERENCE LINE 20 SNR (dBc) -80 -70 -60 -50 -40 -30 -20 -10 0
06709-031
0.2
0.1
0 -90
-4.0 -40
0 -20 0 20 40 60 80 TEMPERATURE (C)
INPUT AMPLITUDE (dBFS)
Figure 32. AD6655-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz, fNCO = 100.49 MHz
95 90 85
SNR/SFDR (dBc)
Figure 35. AD6655-150 Gain and Offset vs. Temperature
0
SFDR = +85C SFDR = +25C SFDR = -40C
SFDR/IMD3 (dBc AND dBFS)
-20 SFDR (dBc) -40 IMD3 (dBc) -60
80 75 70 65 60 0 50
SNR = +25C SNR = +85C SNR = -40C
-80 SFDR (dBFS) -100 IMD3 (dBFS)
100
150
200
250
300
350
400
450
06709-032
-120 -90
-78
-66
-54
-42
-30
-18
-6
INPUT FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 33. AD6655-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with DRVDD = 1.8 V
Figure 36. AD6655-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.12 MHz, fIN2 = 32.12 MHz, fS = 150 MSPS, fNCO = 22 MHz
Rev. 0 | Page 26 of 84
06709-033
0 -90
60
AD6655
0
0 -20 150MSPS 169.12MHz @ -7dBFS 172.12MHz @ -7dBFS SFDR = 85.5dBc (92.5dBFS) fNCO = 177MHz
-20
SFDR/IMD3 (dBc AND dBFS)
SFDR (dBc) -40 IMD3 (dBc) -60
AMPLITUDE (dBFS)
-40 -60 -80 -100 -120 -140 0 5 10 15
-80 SFDR (dBFS) -100 IMD3 (dBFS)
06709-036
-78
-66
-54
-42
-30
-18
-6
20
25
30
35
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 37. AD6655-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.12 MHz, fIN2 = 172.12 MHz, fS = 150 MSPS, fNCO = 177 MHz
0 -20 -40 -60 -80 -100 -120 -140
Figure 40. AD6655-150 Two Tone FFT with fIN1 = 169.12 MHz, fIN2 = 172.12 MHz, fS = 150 MSPS, fNCO = 177 MHz
0 -20 -40 -60 -80 -100 -120 -140 0 7.5 15.0 22.5 30.0 37.5 FREQUENCY (MHz) NPR = 64.5dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz
AMPLITUDE (dBFS)
06709-037
AMPLITUDE (dBFS)
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 38. AD6655-125, Two 64k WCDMA Carriers with fIN = 170 MHz, fS = 122.88 MHz, fNCO = 168.96 MHz
0 -20 -40 -60 -80 -100 -120 -140 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 150MSPS 29.12MHz @ -7dBFS 32.12MHz @ -7dBFS SFDR = 89.1dBc (96.1dBFS) fNCO = 22MHz
SNR/SFDR (dBc)
Figure 41. AD6655-150 Noise Power Ratio (NPR)
95
SFDR (dBc) 85
AMPLITUDE (dBFS)
75
SNR (dBc)
06709-038
65
0
25
50
75
100
125
150
SAMPLE RATE (MSPS)
Figure 39. AD6655-150 Two-Tone FFT with fIN1 = 29.12 MHz, fIN2 = 32.12 MHz, fS = 150 MSPS, fNCO = 22 MHz
Figure 42. AD6655-150 Single-Tone SNR/SFDR vs. Sample Rate (fs) with fIN = 2.3 MHz
Rev. 0 | Page 27 of 84
06709-041
06709-040
06709-039
-120 -90
AD6655
12 0.85 LSB rms 90
10
NUMBER OF HITS (1M)
85 SFDR
SNR/SFDR (dBc)
8
80
6
75 SNR 70
4
2
06709-042
N-3
N-2
N-1
N
N+1
N+2
N+3
0.4
OUTPUT CODE
0.6 0.8 1.0 1.2 INPUT COMMON-MODE VOLTAGE (V)
1.4
Figure 43. AD6655 Grounded Input Histogram
90
Figure 45. AD6655-150 SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30.3 MHz, fNCO = 45 MHz
85
SNR/SFDR (dBc)
SFDR DCS ON 80 SFDR DCS OFF
SNR DCS ON 75 SNR DCS OFF 70 20
30
40
50 DUTY CYCLE (%)
60
70
80
Figure 44. AD6655-150 SNR/SFDR vs. Duty Cycle with fIN = 30.3 MHz, fNCO = 45 MHz
06709-043
Rev. 0 | Page 28 of 84
06709-044
0
65 0.2
AD6655 THEORY OF OPERATION
The AD6655 has two analog input channels, two decimating channels, and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing at the output port(s) as a filtered, decimated digital signal. The dual ADC design can be used for diversity reception of signals, where the ADCs operate identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 150 MHz using appropriate lowpass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD6655 can be used as a baseband receiver, where one ADC is used for I input data, and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. The NCO phase can be set to produce a known offset relative to another channel or device. Programming and control of the AD6655 are accomplished using a 3-bit SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6655 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 46). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In IF undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to Application Note AN-742, Frequency Domain Response of SwitchedCapacitor ADCs; Application Note AN-827, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, "Transformer-Coupled Front-End for Wideband A/D Converters," for more information on this subject (see www.analog.com). In general, the precise values are dependent on the application.
S
ADC ARCHITECTURE
AD6655 architecture consists of a front-end sample-and-hold amplifier (SHA) followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.
CH S CS VIN+ CPIN, PAR VIN- CPIN, PAR CH S H
CS
S
Figure 46. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The output common mode of the reference buffer is set to VCMREF (approximately 1.6 V).
Input Common Mode
The analog inputs of the AD6655 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.55 x AVDD is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 45).
Rev. 0 | Page 29 of 84
06709-048
AD6655
An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 x AVDD). The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD6655. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49). An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver is shown in Figure 50. See the AD8352 data sheet for more information. In addition, if the application requires an amplifier with variable gain, the AD8375 or AD8376 digital variable gain amplifiers (DVGAs) provide good performance driving the AD6655. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 14 displays recommended values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 14. Example RC Network
Frequency Range (MHz) 0 to 70 70 to 200 200 to 300 >300 R Series (, Each) 33 33 15 15 C Differential (pF) 15 5 5 Open
Differential Input Configurations
Optimum performance is achieved while driving the AD6655 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD6655 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
499 1V p-p 49.9 499 R VIN+ C R 499 AVDD
AD8138
0.1F 523
AD6655
06709-049
VIN-
CML
Figure 47. Differential Input Configuration Using the AD8138
For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the analog input, the CML voltage can be connected to the center tap of the secondary winding of the transformer.
R 2V p-p 49.9 R C VIN+
AD6655
VIN- CML
0.1F
Figure 48. Differential Transformer-Coupled Configuration
0.1F 2V p-p 25 PA S S P 0.1F 25 0.1F R C 0.1F R
06709-050
VIN+
AD6655
VIN- CML
06709-051
Figure 49. Differential Double Balun Input Configuration
VCC
0.1F ANALOG INPUT
0
16 1 2
8, 13 11
0.1F 0.1F 200 R VIN+ C R
CD
RD
RG
3 4 5
AD8352
10 14 0.1F 0.1F
200
AD6655
VIN- CML
06709-052
ANALOG INPUT 0.1F
0
0.1F
Figure 50. Differential Input Configuration Using the AD8352
Rev. 0 | Page 30 of 84
AD6655
Single-Ended Input Configuration
A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 51 shows a typical single-ended input configuration.
10F AVDD 1k R 2V p-p 49.9 0.1F 1k C R VIN+
This puts the reference amplifier in a noninverting mode with the VREF output defined as follows:
R2 VREF = 0.5 x 1 + R1 The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
VIN+A/VIN+B VIN-A/VIN-B
AVDD 1k 10F 0.1F 1k
AD6655
VIN-
06709-053
ADC CORE
VREF 1.0F 0.1F SELECT LOGIC
Figure 51. Single-Ended Input Configuration
SENSE
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6655. The input range can be adjusted by varying the reference voltage applied to the AD6655, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.
0.5V
06709-054
AD6655
Figure 52. Internal Reference Configuration
VIN+A/VIN+B VIN-A/VIN-B
Internal Reference Connection
A comparator within the AD6655 detects the potential at the SENSE pin and configures the reference into four possible modes, which are summarized in Table 15. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 52), setting VREF to 1.0 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected externally to the chip, as shown in Figure 53, the switch again sets to the SENSE pin.
ADC CORE
VREF 1.0F 0.1F R2 SENSE SELECT LOGIC
R1
0.5V
06709-055
AD6655
Figure 53. Programmable Reference Configuration
Table 15. Reference Configuration Summary
Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5
R2 (see Figure 53) 0 .5 x 1 + R1
Resulting Differential Span (V p-p) 2 x external reference 1.0 2 x VREF 2.0
1.0
Rev. 0 | Page 31 of 84
AD6655
If the internal reference of the AD6655 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 54 depicts how the internal reference voltage is affected by loading.
0 VREF = 0.5V
via a transformer or capacitors. These pins are biased internally (see Figure 56) and require no external bias.
AVDD
1.2V CLK+ CLK-
REFERENCE VOLTAGE ERROR (%)
-0.25 VREF = 1.0V -0.50
2pF
2pF
06709-058
-0.75
Figure 56. Equivalent Clock Input Circuit
Clock Input Options
-1.00
0
0.5
1.0 LOAD CURRENT (mA)
1.5
2.0
Figure 54. VREF Accuracy vs. Load
06709-056
-1.25
The AD6655 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 57 and Figure 58 show two preferred methods for clocking the AD6655 (at clock rates to up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6655 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD6655, while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance.
Mini-Circuits(R) ADT1-1WT, 1:1Z 0.1F XFMR 100 0.1F 0.1F SCHOTTKY DIODES: HSMS2822
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 55 shows the typical drift characteristics of the internal reference in both 1.0 V and 0.5 V modes.
2.5 2.0
REFERENCE VOLTAGE ERROR (mV)
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -20 0 20 40 60 80
06709-057
0.1F CLOCK INPUT 50
CLK+
ADC AD6655
06709-059
CLK-
Figure 57. Transformer Coupled Differential Clock (Up to 200 MHz)
-2.5 -40
TEMPERATURE (C)
1nF CLOCK INPUT 50 1nF
0.1F CLK+ 0.1F SCHOTTKY DIODES: HSMS2822
Figure 55. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 k load (see Figure 18). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V.
ADC AD6655
06709-157
CLK-
Figure 58. Balun-Coupled Differential Clock (Up to 625 MHz)
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6655 sample clock inputs, CLK+ and CLK-, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK- pins
If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 59. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
Rev. 0 | Page 32 of 84
AD6655
Input Clock Divider
CLOCK INPUT 0.1F 0.1F CLK+ AD951x PECL DRIVER 240 240 100 0.1F
50k
50k
06709-060
CLOCK INPUT
0.1F
ADC AD6655
CLK-
The AD6655 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. If a divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled. The AD6655 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
Figure 59. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 60. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance.
0.1F 0.1F CLK+ AD951x LVDS DRIVER 100 0.1F
Clock Duty Cycle
CLOCK INPUT
50k
50k
06709-061
CLOCK INPUT
0.1F
ADC AD6655
CLK-
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD6655 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6655. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 44. Jitter on the rising edge of the input clock is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.
Figure 60. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 61). CLK+ can be driven directly from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.6 V, making the selection of the drive logic voltage very flexible.
VCC 0.1F CLOCK INPUT 50 1k 1k AD951x CMOS DRIVER OPTIONAL 0.1F 100 CLK+
ADC AD6655
CLK-
06709-062
0.1F
39k
Figure 61. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
Jitter Considerations
VCC CLOCK INPUT 0.1F 50 1k 1k 0.1F AD951x CMOS DRIVER OPTIONAL 0.1F 100 CLK+
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by SNRHF = -10 log[(2 x fIN x tJRMS)2 + 10 ( - SNRLF /10) ]
06709-063
ADC AD6655
CLK-
Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 63.
Rev. 0 | Page 33 of 84
AD6655
75 MEASURED 70 0.20ps 1.25 IAVDD 0.05ps 1.50 TOTAL POWER 0.5 0.6
65
1.00
0.4
60
0.50ps
0.75 IDVDD
0.3
55
1.00ps 1.50ps 2.00ps 2.50ps 3.00ps
06709-064
0.50
0.2
50
0.25 IDRVDD 1000 0 25 50 75 100 125
0.1
1
10
100
INPUT FREQUENCY (MHz)
SAMPLE RATE (MSPS)
Figure 63. SNR vs. Input Frequency and Jitter
Figure 64. AD6655-150 Power and Current vs. Sample Rate
1.00
IAVDD
0.4
0.75
0.3
Refer to Application Note AN501 and Application Note AN756 for more information about jitter performance as it relates to ADCs (see www.analog.com).
0.50 IDVDD 0.25 IDRVDD 0 25 50 75 100 SAMPLE RATE (MSPS)
0.2
0.1
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 64 through Figure 67, the power dissipated by the AD6655 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated by IDRVDD = VDRVDD x CLOAD x fCLK x N
TOTAL POWER (W)
0
Figure 65. AD6655-125 Power and Current vs. Sample Rate
1.25
0.5
1.00 TOTAL POWER 0.75 IAVDD 0.50 IDVDD 0.25 IDRVDD 0 25 50 SAMPLE RATE (MSPS) 75 100
0.4
0.3
This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 64 through Figure 67 was taken using the same operating conditions as those used for the Typical Performance Characteristics, with a 5 pF load on each output driver.
0.2
0.1
Figure 66. AD6655-105 Power and Current vs. Sample Rate
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0
0
SUPPLY CURRENT (A)
where N is the number of output bits (30, in the case of the AD6655, assuming the FD bits are inactive).
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0 125
SUPPLY CURRENT (A)
TOTAL POWER (W)
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD6655. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step.
1.50
0.6
1.25 TOTAL POWER
0.5
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45
0
0 150
SUPPLY CURRENT (A)
TOTAL POWER (W)
SNR (dBc)
AD6655
1.00 0.4
tions requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.
SUPPLY CURRENT (A)
0.75
0.3 TOTAL POWER IAVDD
TOTAL POWER (W)
0.50
0.2
IDVDD 0.25 0.1
The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 16). As detailed in Application Note AN-877, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control.
Table 16. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin AGND (default) AVDD SCLK/DFS Offset binary Twos complement SDIO/DCS DCS disabled DCS enabled
0
20
40 SAMPLE RATE (MSPS)
60
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0
IDRVDD
0 80
Figure 67. AD6655-80 Power and Current vs. Sample Rate
Digital Output Enable Function (OEB)
The AD6655 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SMI SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB pin is low, the output data drivers are enabled. If the SMI SDO/OEB pin is high, the output data drivers are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. OEB can be driven with 1.8 V logic even when DRVDD is at 3.3 V. When using the SPI interface, the data and fast detect outputs of each channel can be independently three-stated by using the output enable bar bit (Bit 4) in Register 0x14.
By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD6655 is placed in power-down mode. In this state, the ADC typically dissipates 2.5 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD6655 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. PDWN can be driven with 1.8 V logic, even when DRVDD is at 3.3 V. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Description section and Application Note AN-877, Interfacing to High Speed ADCs via SPI at www.analog.com for additional details.
Interleaved CMOS Mode
Setting Bit 5 in Register 0x14 enables interleaved CMOS output mode. In this mode, output data is routed through Port A with the ADC Channel A output data present on the rising edge of DCO and the ADC Channel B output data present on the falling edge of DCO.
Timing
The AD6655 provides latched data with a pipeline delay that is dependent on which of the digital back end features are enabled. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6655. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD6655 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade.
DIGITAL OUTPUTS
The AD6655 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. Alternatively, the AD6655 outputs can be configured for either ANSI LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applica-
Data Clock Output (DCO)
The AD6655 also provides data clock output (DCO) intended for capturing the data in an external register. Figure 2 through Figure 6 show a graphical timing description of the AD6655 output modes.
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AD6655
Table 17. Output Data Format
Input (V) VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- Condition (V) < -VREF - 0.5 LSB = -VREF =0 = +VREF - 1.0 LSB > +VREF - 0.5 LSB Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 OR 1 0 0 0 1
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AD6655 DIGITAL DOWNCONVERTER
The AD6655 includes a digital processing section that provides filtering and reduces the output data rate. This digital processing section includes a numerically controlled oscillator (NCO), a half-band decimating filter, an FIR filter, and a second coarse NCO (fADC/8 fixed value) for output frequency translation. Each of these processing blocks (except the decimating half-band filter) has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. These blocks can be configured in five recommended combinations to implement different signal processing functions. a maximum usable bandwidth of 16.5 MHz when using the filter in real mode (NCO bypassed) or a maximum usable bandwidth of 33.0 MHz when using the filter in the complex mode (NCO enabled). The optional fixed-coefficient FIR filter provides additional filtering capability to sharpen the half-band roll-off to enhance the alias protection. It removes the negative frequency images to avoid aliasing negative frequencies for real outputs.
fADC/8 FIXED-FREQUENCY NCO
A fixed fADC/8 NCO is provided to translate the filtered, decimated signal from dc to fADC/8 to allow a real output. Figure 68 to Figure 71 show an example of a 20 MHz input as it is processed by the blocks of the AD6655.
DOWNCONVERTER MODES
Table 18 details the recommended downconverter modes of operation in the AD6655.
Mode 1 2 3 4 5
NCO/Filter Half-band filter only Half-band filter and FIR filter NCO and half-band filter NCO, half-band filter, and FIR filter NCO, half-band filter, FIR filter, and fADC/8 NCO
Output Type Real Real Complex Complex Real
-50
-24
-14
-4 0 4
14
24
50
Figure 68. Example AD6655 Real 20 MHz Bandwidth Input Signal Centered at 14 MHz (fADC = 100 MHz)
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Frequency translation is accomplished with an NCO. Each of the two processing channels shares a common NCO. Amplitude and phase dither can be enabled on chip to improve the noise and spurious performance of the NCO. A phase offset word is available to create a known phase relationship between multiple AD6655s. Because the decimation filter prevents usage of half the Nyquist spectrum, a means is needed to translate the sampled input spectrum into the usable range of the decimation filter. To achieve this, a 32-bit, fine tuning, complex NCO is provided. This NCO/mixer allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing.
-50 -38 -28 -18 -10 0 10 50
Figure 69. Example AD6655 20 MHz Bandwidth Input Signal Tuned to DC Using the NCO (NCO Frequency = 14 MHz)
-50
-38
-28
-18 -10
0
10
50
Figure 70. Example AD6655 20 MHz Bandwidth Input Signal wth the Negative Image Filtered by the Half-Band and FIR Filters
HALF-BAND DECIMATING FILTER AND FIR FILTER
The goal of the AD6655 digital filter block is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. The half-band filter is designed to operate as either a low-pass or high-pass filter and to provide greater than 100 dB of alias protection for 22% of the input rate of the structure. For an ADC sample rate of 150 MSPS, this provides
06709-069
-50
0.25
12.5
22.5
50
Figure 71. Example AD6655 20 MHz Bandwidth Input Signal Tuned to fADC/8 for Real Output
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Table 18. Downconverter Modes
AD6655 NUMERICALLY CONTROLLED OSCILLATOR (NCO)
FREQUENCY TRANSLATION
This processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (NCO). The two channels of the AD6655 share a single NCO. The NCO is optional and can be bypassed by clearing Bit 0 of Register 0x11D. This NCO block accepts a real input from the ADC stage and outputs a frequency translated complex (I and Q) output. The NCO frequency is programmed in Register 0x11E, Register 0x11F, Register 0x120, and Register 0x121. These four 8-bit registers make up a 32-bit unsigned frequency programming word. Frequencies between -CLK/2 and +CLK/2 are represented using the following frequency words:
* * *
PHASE OFFSET
The NCO phase offset register at Address 0x122 and Address 0x123 adds a programmable offset to the phase accumulator of the NCO. This 16-bit register is interpreted as a 16-bit unsigned integer. A 0x00 in this register corresponds to no offset, and a 0xFFFF corresponds to an offset of 359.995. Each bit represents a phase change of 0.005. This register allows multiple NCOs to be synchronized to produce outputs with predictable phase differences. Use the following equation to calculate the NCO phase offset value: NCO_PHASE = 216 x PHASE/360 where: NCO_PHASE is a decimal number equal to the 16-bit binary number to be programmed at Register 0x122 and Register 0x123. PHASE is the desired NCO phase in degrees.
0x8000 0000 represents a frequency given by -CLK/2. 0x0000 0000 represents dc (frequency = 0 Hz). 0x7FFF FFFF represents CLK/2 - CLK/232.
Use the following equation to calculate the NCO frequency:
NCO AMPLITUDE AND PHASE DITHER
The NCO block contains amplitude and phase dither to improve the spurious performance. Amplitude dither improves performance by randomizing the amplitude quantization errors within the angular-to-Cartesian conversion of the NCO. This option reduces spurs at the expense of a slightly raised noise floor. With amplitude dither enabled, the NCO has an SNR of >93 dB and an SFDR of >115 dB. With amplitude dither disabled, the SNR is increased to >96 dB at the cost of SFDR performance, which is reduced to 100 dB. The NCO amplitude dither is recommended and is enabled by setting Bit 1 of Register 0x11D.
NCO_FREQ = 2 x
32
Mod( f , f CLK ) f CLK
where: NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register. f is the desired carrier frequency in hertz (Hz). fCLK is the AD6655 ADC clock rate in hertz (Hz).
NCO SYNCHRONIZATION
The AD6655 NCOs within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 3 and Bit 4 of Register 0x100 allow the NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the NCO to restart at the programmed phase offset value.
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AD6655 DECIMATING HALF-BAND FILTER AND FIR FILTER
The goal of the AD6655 half-band digital filter is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. This filter is designed to operate as either a low-pass or a high-pass filter and to provide >100 dB of alias protection for 11% of the input rate of the structure. Used in conjunction with the NCO and the FIR filter, the halfband filter can provide an effective band-pass. For an ADC sample rate of 150 MSPS, this provides a maximum usable bandwidth of 33 MHz.
0 -10 -20 -30 AMPLITUDE (dBc) -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4
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HALF-BAND FILTER COEFFICIENTS
The 19-tap, symmetrical, fixed-coefficient half-band filter has low power consumption due to its polyphase implementation. Table 19 lists the coefficients of the half-band filter. The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are also listed. Coefficients not listed in Table 19 are 0s.
Table 19. Fixed Coefficients for Half-Band Filter
Coefficient Number C0, C18 C2, C16 C4, C14 C6, C12 C8, C10 C9 Normalized Coefficient 0.0008049 -0.0059023 0.0239182 -0.0755024 0.3066864 0.5 Decimal Coefficient (20-Bit) 844 -6189 25080 -79170 321584 524287
-110 FRACTION OF INPUT SAMPLE RATE
Figure 73. Half-Band Filter High-Pass Response
The half-band filter has a ripple of 0.000182 dB and a rejection of 100 dB. For an alias rejection of 100 dB, the alias protected bandwidth is 11% of the input sample rate. If both the I and the Q paths are used, a complex bandwidth of 22% of the input rate is available. In the event of even Nyquist zone sampling, the half-band filter can be configured to provide a spectral reversal. Setting Bit 2 high in Address 0x103 enables the spectral reversal feature. The half-band decimation phase can be selected such that the half-band filter starts on the first or second sample following synchronization. This shifts the output from the half-band between the two input sample clocks. The decimation phase can be set to 0 or 1, using Bit 3 of Register 0x103.
HALF-BAND FILTER FEATURES
In the AD6655, the half-band filter cannot be disabled. The filter can be set for a low-pass or high-pass response. For a highpass filter, Bit 1 of Register 0x103 should be set; for a low-pass response, this bit should be cleared. The low-pass response of the filter with respect to the normalized output rate is shown in Figure 72, and the high-pass response is shown in Figure 73.
0 -10 -20 -30 AMPLITUDE (dBc) -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4
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FIXED-COEFFICIENT FIR FILTER
Following the half-band filters is a 66-tap, fixed-coefficient FIR filter. This filter is useful in providing extra alias protection for the decimating half-band filter. It is a simple sum-of-products FIR filter with 66 filter taps and 21-bit fixed coefficients. Note that this filter does not decimate. The normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are listed in Table 20. The user can either select or bypass this filter, but the FIR filter can be enabled only when the half-band filter is enabled. Writing Logic 0 to the enable FIR filter bit (Bit 0) in Register 0x102 bypasses this fixed-coefficient filter. The filter is necessary when using the final NCO with a real output; bypassing it when using other configurations results in power savings.
-110 FRACTION OF INPUT SAMPLE RATE
Figure 72. Half-Band Filter Low-Pass Response
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AD6655
Table 20. FIR Filter Coefficients
Coefficient Number C0, C65 C1, C64 C2, C63 C3, C62 C4, C61 C5, C60 C6, C59 C7, C58 C8, C57 C9, C56 C10, C55 C11, C54 C12, C53 C13, C52 C14, C51 C15, C50 C16, C49 C17, C48 C18, C47 C19, C46 C20, C45 C21, C44 C22, C43 C23, C42 C24, C41 C25, C40 C26, C39 C27, C38 C28, C37 C29, C36 C30, C35 C31, C34 C32, C33 Normalized Coefficient 0.0001826 0.0006824 0.0009298 0.0000458 -0.0012689 -0.0008345 0.0011806 0.0011387 -0.0018439 -0.0024557 0.0018063 0.0035825 -0.0021510 -0.0056810 0.0017405 0.0078602 -0.0013437 -0.0110626 -0.0000229 0.0146618 0.0018959 -0.0195594 -0.0053153 0.0255623 0.0104036 -0.0341468 -0.0192165 0.0471258 0.0354118 -0.0728111 -0.0768890 0.1607208 0.4396725 Decimal Coefficient (21-Bit) 383 1431 1950 96 -2661 -1750 2476 2388 -3867 -5150 3788 7513 -4511 -11914 3650 16484 -2818 -23200 -48 30748 3976 -41019 -11147 53608 21818 -71611 -40300 98830 74264 -152696 -161248 337056 922060
COMBINED FILTER PERFORMANCE
The combined response of the half-band filter and the FIR filter is shown in Figure 74. The act of bandlimiting the ADC data with the half-band filter ideally provides a 3 dB improvement in the SNR at the expense of the sample rate and available bandwidth of the output data. As a consequence of finite math, additional quantization noise is added to the system due to truncation in the NCO and half-band. As a consequence of the digital filter rejection of out-of-band noise (assuming no quantization in the filters and with a white noise floor from the ADC), there should be a 3.16 dB improvement in the ADC SNR. However, the added quantization lessens improvement to about 2.66 dB.
0 -10 -20 -30 AMPLITUDE (dBc) -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4
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-110 FRACTION OF INPUT SAMPLE RATE
Figure 74. Half-Band Filter and FIR Filter Composite Response
FINAL NCO
The output of the 32-bit fine tuning NCO is complex and typically centered in frequency around dc. This complex output is carried through the stages of the half-band and FIR filters to provide proper antialiasing filtering. The final NCO provides a means to move this complex output signal away from dc so that a real output can be provided from the AD6655. The final NCO, if enabled, translates the output from dc to a frequency equal to the ADC sampling frequency divided by 8 (fADC/8). This provides the user a decimated output signal centered at fADC/8 in frequency. Optionally, this final NCO can be bypassed, and the dc-centered I and Q values can be output in an interleaved fashion.
SYNCHRONIZATION
The AD6655 half-band filters within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 5 and Bit 6 of Register 0x100 allow the half-bands to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the half-band filter to restart at the programmed decimation phase value.
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AD6655 ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, latency of this function is of major concern. Highly pipelined converters can have significant latency. A good compromise is to use the output bits from the first stage of the ADC for this function. Latency for these output bits is very low, and overall resolution is not highly significant. Peak input signals are typically between full scale and 6 dB to 10 dB below full scale. A 3-bit or 4-bit output provides adequate range and resolution for this function. Using the SPI port, the user can provide a threshold above which an overrange output is active. As long as the signal is below that threshold, the output should remain low. The fast detect outputs can also be programmed via the SPI port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature. In this mode, all 14 bits of the converter are examined in the traditional manner, and the output is high for the condition normally defined as overflow. In either mode, the magnitude of the data is considered in the calculation of the condition (but the sign of the data is not considered). The threshold detection responds identically to positive and negative signals outside the desired range (magnitude).
Table 21. Fast Detect Mode Select Bits Settings
Fast Detect Mode Select bits (Register 0x104[3:1]) 000 001 010 Information Presented on Fast Detect (FD) Pins of Each ADC1, 2 FD[3] FD[2] FD[1] FD[0] ADC fast magnitude (see Table 22) OR ADC fast magnitude (see Table 23) OR F_LT ADC fast magnitude (see Table 24) C_UT F_LT ADC fast magnitude (see Table 24) OR C_UT F_UT F_LT OR F_UT IG DG
011
100 101
1
The fast detect pins are FD0A/FD0B to FD3A/FD3B for the CMOS mode configuration and FD0+/FD0- to FD3+/FD3- for the LVDS mode configuration. 2 See the ADC Overrange (OR) and Gain Switching sections for more information about OR, C_UT, F_UT, F_LT, IG, and DG.
ADC FAST MAGNITUDE
When the fast detect output pins are configured to output the ADC fast magnitude (that is, when the fast detect mode select bits are set to 0b000), the information presented is the ADC level from an early converter stage with a latency of only two clock cycles in CMOS output modes. In LVDS output mode, the fast detect bits have a latency of six cycles in all fast detect modes. Using the fast detect output pins in this configuration provides the earliest possible level indication information. Because this information is provided early in the datapath, there is significant uncertainty in the level indicated. The nominal levels, along with the uncertainty indicated by the ADC fast magnitude, are shown in Table 22. Because the DCO is at one-half the sample rate, the user can obtain all the fast detect information by sampling the fast detect outputs on both the rising and falling edge of DCO (see Figure 2 for timing information).
Table 22. ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits = 000
ADC Fast Magitude on FD[3:0] Pins 0000 0001 0010 0011 0100 0101 0110 0111 1000 Nominal Input Magnitude Below FS (dB) <-24 -24 to -14.5 -14.5 to -10 -10 to -7 -7 to -5 -5 to -3.25 -3.25 to -1.8 -1.8 to -0.56 -0.56 to 0 Nominal Input Magnitude Uncertainty (dB) Minimum to -18.07 -30.14 to -12.04 -18.07 to -8.52 -12.04 to -6.02 -8.52 to -4.08 -6.02 to -2.5 -4.08 to -1.16 -2.5 to FS -1.16 to 0
FAST DETECT OVERVIEW
The AD6655 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level. The function of these pins is programmable via the fast detect mode select bits and the fast detect enable bit in Register 0x104, allowing range information to be output from several points in the internal data path. These output pins can also be set up to indicate the presence of overrange or underrange conditions, according to programmable threshold levels. Table 21 shows the six configurations available for the fast detect pins.
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AD6655
When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins are available. In these modes, the fast detect output pins have a latency of six clock cycles, and the greater of the two input samples is output at the DCO rate. Table 23 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when the ADC fast magnitude is presented on the FD[3:1] pins). Table 23. ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits = 001
ADC Fast Magitude on FD[2:0] Pins 000 001 010 011 100 101 110 111 Nominal Input Magnitude Below FS (dB) <-24 -24 to -14.5 -14.5 to -10 -10 to -7 -7 to -5 -5 to -3.25 -3.25 to -1.8 -1.8 to 0 Nominal Input Magnitude Uncertainty (dB) Minimum to -18.07 -30.14 to -12.04 -18.07 to -8.52 -12.04 to -6.02 -8.52 to -4.08 -6.02 to -2.5 -4.08 to -1.16 -2.5 to 0
an indicator that can be used to quickly insert an attenuator that prevents ADC overdrive.
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast magnitude input level is greater than the level programmed in the coarse upper threshold register (Address 0x105[2:0]). This value is compared with the ADC Fast Magnitude Bits[2:0]. The coarse upper threshold output is output two clock cycles after the level is exceeded at the input and, therefore, provides a fast indication of the input signal level. The coarse upper threshold levels are shown in Table 25. This indicator remains asserted for a minimum of two ADC clock cycles or until the signal drops below the threshold level. Table 25. Coarse Upper Threshold Levels
Coarse Upper Threshold Register[2:0] 000 001 010 011 100 101 110 111 C_UT Is Active When Signal Magnitude Below FS Is Greater Than (dB) <-24 -24 -14.5 -10 -7 -5 -3.25 -1.8
When the fast detect mode select bits are set to 0b010 or 0b011 (that is, when ADC fast magnitude is presented on the FD[2:1] pins), the LSB is not provided. The input ranges for this mode are shown in Table 24. Table 24. ADC Fast Magnitude Nomimal Levels with Fast Detect Mode Select Bits = 010 or 011
ADC Fast Magitude on FD[2:1] Pins 00 01 10 11 Nominal Input Magnitude Below FS (dB) <-14.5 -14.5 to -7 -7 to -3.25 -3.25 to 0 Nominal Input Magnitude Uncertainty (dB) Minimum to -12.04 -18.07 to -6.02 -8.52 to -2.5 -4.08 to 0
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input magnitude exceeds the value programmed in the fine upper threshold register located in Register 0x106 and Register 0x107. The 13-bit threshold register is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC clock latency but is accurate in terms of converter resolution. The fine upper threshold magnitude is defined by the following equation: dBFS = 20 log(Threshold Magnitude/213)
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange condition is determined at the output of the ADC pipeline and, therefore, is subject to a latency of 12 ADC clock cycles. An overrange at the input is indicated by this bit 12 clock cycles after it occurs.
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input magnitude is less than the value programmed in the fine lower threshold register located at Register 0x108 and Register 0x109. The fine lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to ADC clock latency but is accurate in terms of converter resolution. The fine lower threshold magnitude is defined by the following equation: dBFS = 20 log(Threshold Magnitude/213) The operation of the fine upper threshold and fine lower threshold indicators is shown in Figure 75.
GAIN SWITCHING
The AD6655 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging converters are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. Fast detect mode select bits = 010 through fast detect mode select bits = 101 support various combinations of the gain switching options. One such use is to detect when an ADC is about to reach full scale with a particular input condition. The result is to provide
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AD6655
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (Address 0x105). The increment gain indicator, similarly, corresponds to the fine lower threshold bits except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. The dwell time is set by the 16-bit dwell time value located at Address 0x10A and Address 0x10B and is set in units of ADC input clock cycles ranging from 1 to 65,535. The fine lower threshold register is a 13-bit register that is compared with the magnitude at the output of the ADC. This comparison is subject to the ADC clock latency but allows a finer, more accurate comparison. The fine upper threshold magnitude is defined by the following equation: dBFS = 20 log(Threshold Magnitude/213) The decrement gain output works from the ADC fast detect output pins, providing a fast indication of potential overrange conditions. The increment gain uses the comparison at the output of the ADC, requiring the input magnitude to remain below an accurate, programmable level for a predefined period before signaling external circuitry to increase the gain. The operation of the increment gain output and decrement gain output is shown graphically in Figure 75.
UPPER THRESHOLD (COARSE OR FINE)
DWELL TIME TIMER RESET BY RISE ABOVE F_LT
FINE LOWER THRESHOLD
DWELL TIME C_UT OR F_UT* F_LT DG IG
TIMER COMPLETES BEFORE SIGNAL RISES ABOVE F_LT
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY. NOTE: OUTPUTS FOLLOW THE INSTANTEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
Figure 75. Threshold Settings for C_UT, F_UT, F_LT, DG, and IG
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AD6655 SIGNAL MONITOR
The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular threshold. Together, these functions can be used to gain insight into the signal characteristics and to estimate the peak/average ratio or even the shape of the complementary cumulative distribution function (CCDF) curve of the input signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The signal monitor result values can be obtained from the part by reading back internal registers at Address 0x116 to Address 0x11B, using the SPI port or the signal monitor SPORT output. The output contents of the SPI-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register (Address 0x112). Both ADC channels must be configured for the same signal monitor mode. Separate SPI-accessible, 20-bit signal monitor result (SMR) registers are provided for each ADC channel. Any combination of the signal monitor functions can also be output to the user via the serial SPORT interface. These outputs are enabled using the peak detector output enable, the rms magnitude output enable, and the threshold crossing output enable bits in the signal monitor SPORT control register (Address 0x1111). For each signal monitor measurement, a programmable signal monitor period register (SMPR) controls the duration of the measurement. This time period is programmed as the number of input clock cycles in a 24-bit signal monitor period register located at Address 0x113, Address 0x114, and Address 0x115. This register can be programmed with a period from 128 samples to 16.78 (224) million samples. Because the dc offset of the ADC can be significantly larger than the signal of interest (affecting the results from the signal monitor), a dc correction circuit is included as part of the signal monitor block to null the dc offset before measuring the power. current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register (not accessible to the user), which can be read through the SPI port or output through the SPORT serial interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the peak level holding register, and the comparison and update procedure, as explained previously, continues. Figure 76 is a block diagram of the peak detector logic. The SMR register contains the absolute magnitude of the peak detected by the peak detector logic.
FROM MEMORY MAP POWER MONITOR PERIOD REGISTER DOWN COUNTER LOAD FROM INPUT PORTS CLEAR MAGNITUDE STORAGE REGISTER LOAD POWER MONITOR HOLDING REGISTER LOAD TO MEMORY MAP TO INTERRUPT CONTROLLER IS COUNT = 1?
COMPARE A>B
Figure 76. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
In this mode, the root-mean-square (rms) or mean-square (ms) magnitude of the input port signal is integrated (by adding an accumulator) over a programmable time period (determined by SMPR) to give the rms or ms magnitude of the input signal. This mode is set by programming Logic 0 in the signal monitor mode bits of the signal monitor control register or by setting the rms magnitude output enable bit in the signal monitor SPORT control register. The 24-bit SMPR, representing the period over which integration is performed, must be programmed before activating this mode. After enabling the rms/ms magnitude mode, the value in the SMPR is loaded into a monitor period timer, and the countdown is started immediately. Each input sample is converted to floating-point format and squared. It is then converted to 11-bit, fixed-point format and added to the contents of the 24-bit accumulator. The integration continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the square root of the value in the accumulator is taken and transferred (after some formatting) to the signal monitor holding register, which can be read through the SPI port or output through the SPORT serial port. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted.
PEAK DETECTOR MODE
The magnitude of the input port signal is monitored over a programmable time period (determined by SMPR) to give the peak value detected. This function is enabled by programming a Logic 1 in the signal monitor mode bits of the signal monitor control register or by setting the peak detector output enable bit in the signal monitor SPORT control register. The 24-bit SMPR must be programmed before activating this mode. After enabling this mode, the value in the SMPR is loaded into a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the value in the internal peak level holding register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the peak level holding register is set to the
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06709-074
AD6655
In addition, the first input sample signal power is updated in the accumulator, and the accumulation continues with the subsequent input samples. Figure 77 illustrates the rms magnitude monitoring logic.
FROM MEMORY MAP POWER MONITOR PERIOD REGISTER DOWN COUNTER LOAD FROM INPUT PORTS CLEAR ACCUMULATOR LOAD POWER MONITOR HOLDING REGISTER TO MEMORY MAP
06709-075
When the monitor period timer reaches a count of 1, the value in the internal count register is transferred to the signal monitor holding register, which can be read through the SPI port or output through the SPORT serial port. The monitor period timer is reloaded with the value in the SMPR register, and the countdown is restarted. The internal count register is also cleared to a value of 0. Figure 78 illustrates the threshold crossing logic. The value in the SMR register is the number of samples that have a magnitude greater than the threshold register.
FROM MEMORY MAP POWER MONITOR PERIOD REGISTER DOWN COUNTER LOAD FROM INPUT PORTS FROM MEMORY MAP CLEAR A COMPARE A>B B
06709-076
TO INTERRUPT CONTROLLER IS COUNT = 1?
Figure 77. ADC Input RMS Magnitude Monitoring Block Diagram
TO INTERRUPT CONTROLLER IS COUNT = 1?
For rms magnitude mode, the value in the signal monitor result (SMR) register is a 20-bit fixed-point number. The following equation can be used to determine the rms magnitude in dBFS from the MAG value in the register. Note that if the signal monitor period (SMP) is a power of 2, the second term in the equation becomes 0. MAG SMP RMS Magnitude = 20 log 20 - 10 log ceil [log 2 (SMP )] 2 2 For ms magnitude mode, the value in the SMR is a 20-bit fixedpoint number. The following equation can be used to determine the ms magnitude in dBFS from the MAG value in the register. Note that if the SMP is a power of 2, the second term in the equation becomes 0. MAG SMP MS Magnitude = 10 log 20 - 10 log ceil [log 2 (SMP )] 2 2
LOAD POWER MONITOR HOLDING REGISTER
COMPARE A>B
TO MEMORY MAP
UPPER THRESHOLD REGISTER
Figure 78. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two control bits are provided in the signal monitor control register. They are the signal monitor enable bit and the complex power calculation mode enable bit.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112, enables operation of the signal monitor block. If the signal monitor function is not needed in a particular application, this bit should be cleared to conserve power.
THRESHOLD CROSSING MODE
In the threshold crossing mode of operation, the magnitude of the input port signal is monitored over a programmable time period (given by SMPR) to count the number of times it crosses a certain programmable threshold value. This mode is set by programming Logic 1x (where x is a don't care bit) in the signal monitor mode bits of the signal monitor control register or by setting the threshold crossing output enable bit in the signal monitor SPORT control register. Before activating this mode, the user needs to program the 24-bit SMPR and the 13-bit upper threshold register for each individual input port. The same upper threshold register is used for both signal monitoring and gain control (see the ADC Overrange and Gain Control section). After entering this mode, the value in the SMPR is loaded into a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the upper threshold register (programmed previously) on each input clock cycle. If the input signal has a magnitude greater than the upper threshold register, the internal count register is incremented by 1. The initial value of the internal count register is set to 0. This comparison and incrementing of the internal count register continues until the monitor period timer reaches a count of 1.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing the I data and Channel B is digitizing the Q data for a complex input signal (or vice versa). In this mode, the power reported is equal to I 2 + Q2 This result is presented in the Signal Monitor DC Value Channel A register if the signal monitor mode bits are set to 00. The Signal Monitor DC Value Channel B register continues to compute the Channel B value.
DC CORRECTION
Because the dc offset of the ADC may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the ADC is digitizing a time-varying signal with significant dc content, such as GSM.
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AD6655
DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing the 4-bit dc correction control register located at Register 0x10C, Bits[5:2]. The following equation can be used to compute the bandwidth value for the dc correction circuit:
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins: the SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and SMI SDO (SPORT data output). The SPORT is the master and drives all three SPORT output pins on the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4, or 1/8 the ADC clock rate, based on the SPORT controls. The SMI SCLK can also be gated off when not sending any data, based on the SPORT SMI SCLK sleep bit. Using this bit to disable the SMI SCLK when it is not needed can reduce any coupling errors back into the signal path, if these prove to be a problem in the system. Doing so, however, has the disadvantage of spreading the frequency content of the clock. If desired the SMI SCLK can be left running to ease frequency planning.
DC _ Corr _ BW = 2 -k -14 x
f CLK 2x
where: k is the 4-bit value programmed in Bits[5:2] of Register 0x10C (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD6655 ADC sample rate in hertz (Hz).
DC Correction Readback
The current dc correction value can be read back in Register 0x10D and Register 0x10E for Channel A and Register 0x10F and Register 0x110 for Channel B. The dc correction value is a 14-bit value that can span the entire input range of the ADC.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the start of a frame. One SPORT frame includes data from both datapaths. The data from Datapath A is sent just after the frame sync, followed by data from Datapath B.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the DC correction at its current state and continues to use the last updated value as the dc correction value. Clearing this bit restarts dc correction and adds the currently calculated value to the data.
SMI SDO
The SMI SDO is the serial data output of the block. The data is sent MSB first on the next positive edge after the SMI SDFS. Each data output block includes one or more of rms magnitude, peak level, and threshold crossing values from each datapath in the stated order. If enabled, the data is sent, rms first, followed by peak and threshold, as shown in Figure 79.
GATED, BASED ON CONTROL
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in the signal monitor calculations. The calculated dc correction value can be added to the output data signal path by setting Bit 1 of Register 0x10C.
SMI SCLK SMI SDFS SMI SDO MSB
RMS/MS CH A LSB
PK CH A
THR CH A
MSB
RMS/MS CH B LSB
PK CH B
THR CH B
RMS/MS CH A
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20 CYCLES
16 CYCLES
16 CYCLES
20 CYCLES
16 CYCLES
16 CYCLES
Figure 79. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
GATED, BASED ON CONTROL SMI SCLK
SMI SDFS
SMI SDO
MSB
RMS/MS CH A LSB
THR CH A
MSB
RMS/MS CH B LSB
THR CH B
RMS/MS CH A
06709-078
20 CYCLES
16 CYCLES
20 CYCLES
16 CYCLES
Figure 80. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
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AD6655 CHANNEL/CHIP SYNCHRONIZATION
The AD6655 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider, NCO, half-band filters, and signal monitor block can be synchronized using the SYNC input. Each of these blocks, except for the signal monitor, can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be synchronized to the input clock signal. The SYNC input should be driven using a single-ended CMOS type signal.
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AD6655 SERIAL PORT INTERFACE (SPI)
The AD6655 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see Application Note AN-877, Interfacing to High Speed ADCs via SPI at www.analog.com.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Table 26). The SCLK/DFS (serial clock) pin is used to synchronize the read and write data presented from/to the ADC. The SDIO/DCS (serial data input/ output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active-low control that enables or disables the read and write cycles.
Table 26. Serial Port Interface Pins
Pin SCLK SDIO Function Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip Select Bar. An active-low control that gates the read and write cycles.
HARDWARE INTERFACE
The pins described in Table 26 comprise the physical interface between the user programming device and the serial port of the AD6655. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in Application Note AN-812, MicrocontrollerBased Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6655 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD6655.
CSB
The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 81 and Table 9. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 bit and the W1 bit.
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AD6655
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select should be connected to AVDD, which disables the serial port interface.
Table 27. Mode Selection
Pin SDIO/DCS External Voltage AVDD (default) AGND SCLK/DFS AVDD AGND (default) AVDD AGND (default) AVDD AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs in high impedance Outputs enabled Chip in power-down or standby Normal operation
SPI ACCESSIBLE FEATURES
Table 28 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in Application Note AN-877, Interfacing to High Speed ADCs via SPI (see www.analog.com). The AD6655 part-specific features are described in the Memory Map Register Description section.
Table 28. Features Accessible Using the SPI
Feature Name Mode Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage
SMI SDO/OEB
SMI SCLK/PDWN
tDS tS
CSB
tHIGH tDH tLOW
tCLK
tH
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON'T CARE
Figure 81. Serial Port Interface Timing Diagram
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06709-079
AD6655 MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x18); and the digital feature control registers (Address 0x100 to Address 0x123). The memory map register table (see Table 29) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF select register, has a hexadecimal default value of 0xC0. This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see Application Note AN-877, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, from Register 0x100 to Register 0x123, are documented in the Memory Map Register Description section.
Logic Levels
An explanation of logic level terminology follows: * * "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." "Clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
Transfer Register Map
Address 0x08 to Address 0x18 and Address 0x11E to Address 0x123 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 29 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 29 affect the entire part or the channel features where independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.
Open Locations
All address and bit locations that are not included in Table 29 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written.
Default Values
After the AD6655 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 29.
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AD6655
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 29 are not currently supported for this device.
Table 29. Memory Map Registers
Addr. Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 0 SPI Port Configuration (Global) Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles are mirrored so that LSB- first or MSB-first mode registers correctly, regardless of shift mode Default is unique chip ID, different for each device; this is a read-only register Speed grade ID used to differentiate devices; this is a read-only register Bits are set to determine which device on chip receives the next write command; applies to local registers Synchronously transfers data from the master shift register to the slave Determines various generic modes of chip operation
0x01
Chip ID (Global)
8-bit Chip ID[7:0] (AD6655 = 0x0D) (default)
0x0D
0x02
Chip Grade (Global)
Open
Open
Speed Grade ID[4:3] 00 = 150 MSPS 01 = 125 MSPS 10 = 105 MSPS 11 = 80 MSPS
Open
Open
Open
Open
Channel Index and Transfer Registers 0x05 Open Channel Index
Open
Open
Open
Open
Open
Data Channel B (default)
Data Channel A (default)
0x03
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Function Registers 0x08 Power Modes
Open
Open
0x09
Global Clock (Global) Clock Divide (Global)
Open
Open
External powerdown pin function (global) 0 = pdwn 1 = stndby Open
Open
Open
Open
Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation Duty cycle stabilize (default) Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Open
0x00
Open
Open
Open
0x01
0x0B
Open
Open
Open
Open
Open
0x00
Clock divide values other than 000 automatically activate duty cycle stabilization
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AD6655
Addr. (Hex) 0x0D Register Name Test Mode (Local) Bit 7 (MSB) Open Bit 6 Open Bit 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Open Output test mode Reset Reset PN long PN short 000 = off (default) sequence sequence 001 = midscale short 010 = positive FS 011 = negative FS 100 = alternating checkerboard 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle Offset adjust in LSBs from +31 to -32 (twos complement format) Interleaved CMOS (global) Output enable bar (local) Open Output invert (local) 00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary (local) Default Value (Hex) 0x00 Default Notes/ Comments When enabled, the test data is placed on the output pins in place of ADC output data
0x10 0x14
Offset Adjust (Local) Output Mode
Open Drive strength 0 V to 3.3 V CMOS or ANSI LVDS; 1 V to 1.8 V CMOS or reduced LVDS (global) Invert DCO clock
Open Output type 0 = CMOS 1 = LVDS (global)
0x00 0x00 Configures the outputs and the format of the data
0x16
Clock Phase Control (Global)
Open
Open
Open
0x17
DCO Output Delay (Global)
Open
Open
Open
0x18
Reference voltage selection 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) Digital Feature Control Registers 0x100 Sync Control Signal Half-band monitor next sync (Global) sync only enable 0x101 fS/8 Output Mix Control (Global) FIR Filter and Output Mode Control (Global) Digital Filter Control (Global) Open Open
VREF Select (Global)
Open
Open
Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles DCO clock delay (delay = 2500 ps x register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps ... 11110 = 2419 ps 11111 = 2500 ps Open Open Open Open
Open
0x00
Allows selection of clock delays into the input divider
0x00
0xC0
Half-band sync enable
NCO32 next sync only
NCO32 sync enable
fS/8 start state
Open
Clock divider next sync only Open
Clock divider sync enable fS/8 next sync only Complex output enable
Master sync enable
0x00
fS/8 sync enable FIR filter enable
0x00
0x102
Open
Open
Open
Open
0x103
Open
Open
Open
Open
FIR gain 0 = gain of 2 1 = gain of 1 Half-band decimation phase
fS/8 output mix disable Spectral reversal
0x00
High-pass/ low-pass select
Open
0x01
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AD6655
Addr. (Hex) 0x104 Register Name Fast Detect Control (Local) Coarse Upper Threshold (Local) Fine Upper Threshold Register 0 (Local) Fine Upper Threshold Register 1 (Local) Fine Lower Threshold Register 0 (Local) Fine Lower Threshold Register 1 (Local) Increase Gain Dwell Time Register 0 (Local) Increase Gain Dwell Time Register 1 (Local) Signal Monitor DC Correction Control (Global) Signal Monitor DC Value Channel A Register 0 (Global) Signal Monitor DC Value Channel A Register 1 (Global) Signal Monitor DC Value Channel B Register 0 (Global) Signal Monitor DC Value Channel B Register 1 (Global) Signal Monitor SPORT Control (Global) Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Bit 2 Bit 1 Fast Detect Mode Select[2:0] Bit 0 (LSB) Fast detect enable Default Value (Hex) 0x00 Default Notes/ Comments
0x105
Open
Open
Open
Open
Open
Coarse Upper Threshold[2:0]
0x00
0x106
Fine Upper Threshold[7:0]
0x00
0x107
Open
Open
Open
Fine Upper Threshold[12:8]
0x00
0x108
Fine Lower Threshold[7:0]
0x00
0x109
Open
Open
Open
Fine Lower Threshold[12:8]
0x00
0x10A
Increase Gain Dwell Time[7:0]
0x00
In ADC clock cycles
0x10B
Increase Gain Dwell Time[15:8]
0x00
In ADC clock cycles
0x10C
Open
DC correction freeze
DC Correction Bandwidth(k:[3:0])
DC correction for signal path enable
DC correction for signal monitor enable
0x00
0x10D
DC Value Channel A[7:0]
Read only
0x10E
Open
Open
DC Value Channel A[13:8]
Read only
0x10F
DC Value Channel B[7:0]
Read only
0x110
Open
Open
DC Value Channel B[13:8]
Read only
0x111
Open
RMS magnitude output enable
Peak detector output enable
Threshold crossing output enable
SPORT SMI SCLK divide 00 = Undefined 01 = divide by 2 10 = divide by 4 11 = divide by 8
SPORT SMI SCLK sleep
Signal monitor SPORT output enable
0x04
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AD6655
Addr. (Hex) 0x112 Register Name Signal Monitor Control (Global) Bit 7 (MSB) Complex power calculation mode enable Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Signal monitor rms/ms select 0 = rms 1 = ms Bit 2 Bit 1 Signal monitor mode 00 = rms/ms magnitude 01 = peak detector 10 = threshold crossing 11 = threshold crossing Bit 0 (LSB) Signal monitor enable Default Value (Hex) 0x00 Default Notes/ Comments
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11D
Signal Monitor Period Register 0 (Global) Signal Monitor Period Register 1 (Global) Signal Monitor Period Register 2 (Global) Signal Monitor Result Channel A Register 0 (Global) Signal Monitor Result Channel A Register 1 (Global) Signal Monitor Result Channel A Register 2 (Global) Signal Monitor Result Channel B Register 0 (Global) Signal Monitor Result Channel B Register 1 (Global) Signal Monitor Result Channel B Register 2 (Global) NCO Control (Global)
Signal Monitor Period[7:0]
0x80
In ADC clock cycles
Signal Monitor Period[15:8]
0x00
I In ADC clock cycles
Signal Monitor Period[23:16]
0x00
In ADC clock cycles
Signal Monitor Result Channel A[7:0]
Read only
Signal Monitor Result Channel A[15:8]
Read only
Open
Open
Open
Open
Signal Monitor Result Channel A[19:16]
Read only
Signal Monitor Result Channel B[7:0]
Read only
Signal Monitor Result Channel B[15:8]
Read only
Open
Open
Open
Open
Signal Monitor Result Channel B[19:16]
Read only
Open
Open
Open
Open
Open
NCO32 phase dither enable
NCO32 amplitude dither enable
NCO32 enable
0x00
0x11E 0x11F 0x120
NCO Frequency 0 NCO Frequency 1 NCO Frequency 2
NCO Frequency Value[7:0] NCO Frequency Value[15:8] NCO Frequency Value[23:16]
0x00 0x00 0x00
Rev. 0 | Page 54 of 84
AD6655
Addr. (Hex) 0x121 0x122 0x123 Register Name NCO Frequency 3 NCO Phase Offset 0 NCO Phase Offset 1 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 NCO Frequency Value[31:24] NCO Phase Value[7:0] NCO Phase Value[15:8] Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 0x00 0x00 0x00 Default Notes/ Comments
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00 to Register 0xFF, see Application Note AN-877, Interfacing to High Speed ADCs via SPI, at www.analog.com.
Bit 1--Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is passed when Bit 1 and Bit 0 are high. This is continuous sync mode.
SYNC Control (Register 0x100) Bit 7--Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external sync input to the signal monitor block. The sync signal is passed when Bit 7 and Bit 0 are high. This is continuous sync mode.
Bit 0--Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Bit 6--Half-Band Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the halfband sync enable bit (Register 0x100, Bit 5) are high, Bit 6 allows the NCO32 to synchronize following the first sync pulse it receives and ignore the rest. If Bit 6 is set, Bit 5 of Register 0x100 resets after this sync occurs.
fS/8 Output Mix Control (Register 0x101) Bits[7:6]--Reserved Bits[5:4]--fS/8 Start State
Bit 5 and Bit 4 set the starting phase of the fS/8 output mix.
Bits[3:2]--Reserved Bit 1--fS/8 Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the fS/8 sync enable bit (Register 0x101, Bit 0) are high, Bit 1 allows the fS/8 output mix to synchronize following the first sync pulse it receives and ignore the rest. Bit 0 of Register 0x100 resets after it synchronizes.
Bit 5--Half-Band Sync Enable
Bit 5 gates the sync pulse to the half-band filter. When Bit 5 is set high, the sync signal causes the half-band to resynchronize, starting at the half-band decimation phase selected in Register 0x103, Bit 3. This sync is active only when the master sync enable bit (Register 0x100, Bit 0) is high. This is continuous sync mode.
Bit 0--fS/8 Sync Enable
Bit 0 gates the sync pulse to the fS/8 output mix. This sync is active only when the master sync enable bit (Register 0x100, Bit 0) is high. This is continuous sync mode.
Bit 4--NCO32 Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the NCO32 sync enable bit (Register 0x100, Bit 3) are high, Bit 4 allows the NCO32 to synchronize following the first sync pulse it receives and ignore the rest. Bit 3 of Register 0x100 resets after a sync occurs if Bit 4 is set.
FIR Filter and Output Mode Control (Register 0x102) Bits[7:4]--Reserved Bit 3--FIR Gain
When Bit 3 is set high, the FIR filter path, if enabled, has a gain of 1. When Bit 3 set low, the FIR filter path has a gain of 2.
Bit 3--NCO32 Sync Enable
Bit 3 gates the sync pulse to the 32-bit NCO. When this bit is set high, the sync signal causes the NCO to resynchronize, starting at the NCO phase offset value. This sync is active only when the master sync enable bit (Register 0x100, Bit 0) is high. This is continuous sync mode.
Bit 2--fS/8 Output Mix Disable
Bit 2 disables the fS/8 output mix when enabled. Bit 2 should be set along with Bit 1 to enable complex output mode.
Bit 1--Complex Output Mode Enable
Setting Bit 1 high enables complex output mode.
Bit 2--Clock Divider Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the clock divider sync enable bit (Register 0x100, Bit 1) are high, Bit 2 allows the clock divider to synchronize following the first sync pulse it receives and ignores the rest. Bit 1 of Register 0x100 resets after it synchronizes.
Bit 0--FIR Filter Enable
When set high, Bit 0 enables the FIR filter. When Bit 0 is cleared, the FIR filter is bypassed and shut down for power savings.
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AD6655
Digital Filter Control (Register 0x103) Bits[7:4]--Reserved Bit 3--Half-Band Decimation Phase
When set high, Bit 3 uses the alternate phase of the decimating half-band filter. block. If the ADC magnitude is less than this threshold value, the F_LT indicator is set.
Bit 2--Spectral Reversal
Bit 2 enables the spectral reversal feature of the half-band filter.
Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10B, Bits[7:0]--Increase Gain Dwell Time Bits[15:8] Register 0x10A, Bits[7:0]--Increase Gain Dwell Time Bits[7:0]
These register values set the minimum time in ADC sample clock cycles (after clock divider) that a signal needs to stay below the fine lower threshold limit before the F_LT and IG are asserted high.
Bit 1--High-Pass/Low-Pass Select
Bit 1 enables the high-pass mode of the half-band filter when set high. Setting this bit low enables the low-pass mode (default).
Bit 0--Reserved
Bit 0 reads back as a 1.
Fast Detect Control (Register 0x104) Bits[7:4]--Reserved Bits[3:1]--Fast Detect Mode Select
Bits[3:1] set the mode of the fast detect output bits according to Table 29.
Signal Monitor DC Correction Control (Register 0x10C) Bit 7--Reserved Bit 6--DC Correction Freeze
When Bit 6 is set high, the dc correction is no longer updated to the signal monitor block, which holds the last dc value calculated.
Bit 0--Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the FD outputs are disabled, the outputs go into a high impedance state. In LVDS mode when the outputs are interleaved, the outputs go high-Z only if both channels are turned off (power-down/ standby/output disabled). If only one channel is turned off (power-down/standby/output disabled), the fast detect outputs repeat the data of the active channel.
Bits[5:2]--DC Correction Bandwidth
Bits[5:2] set the averaging time of the signal monitor dc correction function. This 4-bit word sets the bandwidth of the correction block, according to the following equation:
DC _ Corr _ BW = 2- k - 14 x fCLK 2x
Coarse Upper Threshold (Register 0x105) Bits[7:3]--Reserved Bits[2:0]--Coarse Upper Threshold
These bits set the level required to assert the coarse upper threshold indication (see Table 25).
where: k is the 4-bit value programmed in Bits[5:2] of Register 0x10C (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). fCLK is the AD6655 ADC sample rate in hertz (Hz).
Bit 1--DC Correction for Signal Path Enable
Setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path.
Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x107, Bits[7:5]--Reserved Register 0x107, Bits[4:0]--Fine Upper Threshold Bits[12:8] Register 0x106, Bits[7:0]--Fine Upper Threshold Bits[7:0]
These registers provide a fine upper limit threshold. The 13-bit value is compared to the 13-bit magnitude from the ADC block. If the ADC magnitude exceeds this threshold value, the F_UT indicator is set.
Bit 0--DC Correction for Signal Monitor Enable
This bit enables the dc correction function in the signal monitor block. The dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. Removing this dc from the measurement allows a more accurate power reading.
Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x109, Bits[7:5]--Reserved Register 0x109, Bits[4:0]--Fine Lower Threshold Bits[12:8] Register 0x108, Bits[7:0]--Fine Lower Threshold Bits[7:0]
These registers provide a fine lower limit threshold. This 13-bit value is compared with the 13-bit magnitude from the ADC
Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10E, Bits[7:6]--Reserved Register 0x10E, Bits[5:0]--DC Value Channel A[13:8] Register 0x10D, Bits[7:0]--DC Value Channel A[7:0]
These read-only registers hold the latest dc offset value computed by the signal monitor for Channel A.
Rev. 0 | Page 56 of 84
AD6655
Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x110, Bits[7:6]--Reserved Register 0x110, Bits[5:0]--Channel B DC Value Bits[13:8] Register 0x10F, Bits[7:0]--Channel B DC Value Bits [7:0]
These read-only registers hold the latest dc offset value computed by the signal monitor for Channel B.
Bit 0--Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x115 Bits[7:0]--Signal Monitor Period[23:16] Register 0x114 Bits[7:0]--Signal Monitor Period[15:8] Register 0x113 Bits[7:0]--Signal Monitor Period[7:0]
This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. The minimum value for this register is 128 cycles (programmed values less than 128 revert to 128).
Signal Monitor SPORT Control (Register 0x111) Bit 7--Reserved Bit 6--RMS/MS Magnitude Output Enable
Bit 6 enables the 20-bit rms or ms magnitude measurement as output on the SPORT.
Bit 5--Peak Detector Output Enable
Bit 5 enables the 13-bit peak measurement as output on the SPORT.
Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x118, Bits[7:4]--Reserved Register 0x118, Bits[3:0]--Signal Monitor Result Channel A[19:16] Register 0x117, Bits[7:0]--Signal Monitor Result Channel A[15:8] Register 0x116, Bits[7:0]--Signal Monitor Result Channel A[7:0]
This 20-bit value contains the power value calculated by the signal monitor block for Channel A. The content is dependent on the settings in Register 0x112, Bits[2:1].
Bit 4--Threshold Crossing Output Enable
Bit 4 enables the 13-bit threshold measurement as output on the SPORT.
Bits[3:2]--SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio from the input clock. A value of 0x01 sets divide by 2 (default), a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Bit 1--SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the signal monitor block has no data to transfer.
Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x11B, Bits[7:4]--Reserved Register 0x11B, Bits[3:0]--Signal Monitor Result Channel B[19:16] Register 0x11A, Bits[7:0]--Signal Monitor Result Channel B[15:8] Register 0x119, Bits[7:0]--Signal Monitor Result Channel B[7:0]
This 20-bit value contains the power value calculated by the signal monitor block for Channel B. The content is dependent on the settings in Register 0x112, Bits[2:1].
Bit 0--Signal Monitor SPORT Output Enable
When set, Bit 0 enables the signal monitor SPORT output to begin shifting out the result data from the signal monitor block.
Signal Monitor Control (Register 0x112) Bit 7--Complex Power Calculation Mode Enable
This mode assumes I data is present on one channel and Q data is present on the alternate channel. The result reported is the complex power measured as I 2 + Q2
Bits[6:4]--Reserved Bit 3--Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting Bit 3 high selects ms power measurement mode.
NCO Control (Register 0x11D) Bits[7:3]--Reserved Bit 2--NCO32 Phase Dither Enable
When Bit 2 is set, phase dither in the NCO is enabled. When Bit 2 is cleared, phase dither is disabled.
Bits[2:1]--Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for data output to registers at Address 0x116 through Address 0x11B. Setting these bits to 0x00 selects rms/ms magnitude output, setting these bits to 0x01 selects peak detector output, and setting 0x10 or 0x11 selects threshold crossing output.
Bit 1--NCO32 Amplitude Dither Enable
When Bit 1 is set, amplitude dither in the NCO is enabled. When Bit 1 is cleared, amplitude dither is disabled.
Rev. 0 | Page 57 of 84
AD6655
Bit 0--NCO32 Enable
When Bit 0 is set, this bit enables the 32-bit NCO operating at the frequency programmed into the NCO frequency register. When Bit 0 is cleared, the NCO is bypassed and shuts down for power savings.
NCO Phase Offset (Register 0x122 and Register 0x123) Register 0x122, Bits[7:0]--NCO Phase Value[7:0] Register 0x123, Bits[7:0]--NCO Phase Value[15:8]
The 16-bit value programmed into the NCO phase value register is loaded into the NCO block each time the NCO is started or when an NCO SYNC signal is received. This process allows the NCO to be started with a known nonzero phase. Use the following equation to calculate the NCO phase offset value: NCO_PHASE = 216 x PHASE/360 where: NCO_PHASE is a decimal number equal to the 16-bit binary number to be programmed at Register 0x122 and Register 0x123. PHASE is the desired NCO phase in degrees.
NCO Frequency (Register 0x11E to Register 0x121) Register 0x11E, Bits[7:0]--NCO Frequency Value[7:0] Register 0x11F, Bits[7:0]--NCO Frequency Value[15:8] Register 0x120, Bits[7:0]--NCO Frequency Value[23:16] Register 0x121, Bits[7:0]--NCO Frequency Value[31:24]
This 32-bit value is used to program the NCO tuning frequency. The frequency value to be programmed is given by the following equation:
NCO_FREQ = 232 x Mod ( f , fCLK ) fCLK
where: NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register. f is the desired carrier frequency in hertz (Hz). fCLK is the AD6655 ADC clock rate in hertz (Hz).
Rev. 0 | Page 58 of 84
AD6655 APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system-level design and layout of the AD6655, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. For the specifications provided in Table 2, the fS/2 spur, if in band, is excluded from the SNR values. It is treated as a harmonic, in terms of SNR. The fS/2 level is included in the SFDR and worst other specifications.
-60
Power and Ground Recommendations
When connecting power to the AD6655, it is recommended that two separate 1.8 V supplies be used: one supply should be used for analog (AVDD) and digital (DVDD), and a separate supply should be used for the digital outputs (DRVDD). The AVDD and DVDD supplies, while derived from the same source, should be isolated with a ferrite bead or filter choke and separate decoupling capacitors. The designer can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the pins of the part with minimal trace length. A single PCB ground plane should be sufficient when using the AD6655. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved.
SFDR AND fS/2 SPUR (dBFS)
-70
-80
-SFDR
-90
-100 fS/2 SPUR -110
06709-083
-120
0
50
100
150
200
250
300
350
400
450
500
INPUT FREQUENCY (MHz)
Figure 82. AD6655-125 SFDR and fS/2 Spurious Level vs. Input Frequency (fIN) with DRVDD = 1.8 V Parallel CMOS Output Mode
-60
-70
SFDR AND fS/2 SPUR (dBFS)
fS/2 Spurious
Because the AD6655 output data rate is at one-half the sampling frequency, there is significant fS/2 energy in the outputs of the part. If this fS/2 spur falls in band, care must be taken to ensure that this fS/2 energy does not couple into either the clock circuit or the analog inputs of the AD6655. When fS/2 energy is coupled in this fashion, it appears as a spurious tone reflected around fS/4, 3fS/4, 5fS/4, and so on. For example, in a 125 MSPS sampling application with a 90 MHz single-tone analog input, this energy generates a tone at 97.5 MHz. In this example, the center of the Nyquist zone is 93.75 MHz; therefore, the 90 MHz input signal is 3.75 MHz from the center of the Nyquist zone. As a result, the fS/2 spurious tone appears at 97.5 MHz, or 3.75 MHz above the center of the Nyquist zone. These frequencies are then tuned by the NCOs before being output by the AD6655. Depending on the relationship of the IF frequency to the center of the Nyquist zone, this spurious tone may or may not exist in the AD6655 output band. Some residual fS/2 energy is present in the AD6655, and the level of this spur is typically below the level of the harmonics at clock rates of 125 MSPS and below. Figure 82 shows a plot of the fS/2 spur level vs. analog input frequency for the AD6655-125. At sampling rates above 125 MSPS, the fS/2 spur level increases and is at a higher level than the worst harmonic, as shown in Figure 83, which shows the AD6655-150 fS/2 levels.
fS/2 SPUR -80
-90 -SFDR -100
-110
06709-084
-120
0
50
100
150
200
250
300
350
400
450
500
ANALOG INPUT FREQUENCY (MHz)
Figure 83. AD6655-150 SFDR and fS/2 Spurious Level vs. Input Frequency (fIN) with DRVDD = 1.8 V Parallel CMOS Output Mode
Operating the part with a 1.8 V DRVDD voltage rather than a 3.3 V DRVDD lowers the fS/2 spur. In addition, using LVDS, CMOS interleaved, or CMOS IQ output modes also reduces the fS/2 spurious level.
LVDS Operation
The AD6655 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed using the SPI configuration registers after power-up. When the AD6655 powers up in CMOS mode with LVDS termination resistors (100 ) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD6655, but it should be taken into account when considering the maximum DRVDD current for the part.
Rev. 0 | Page 59 of 84
AD6655
To avoid this additional DRVDD current, the AD6655 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed into LVDS mode via the SPI port, the OEB pin can be taken low to enable the outputs.
CML
The CML pin should be decoupled to ground with a 0.1 F capacitor, as shown in Figure 48.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD6655 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, refer to Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) (see www.analog.com).
RBIAS
The AD6655 requires that a 10 k resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6655 to keep these signals from transitioning at the converter inputs during critical sampling periods.
Rev. 0 | Page 60 of 84
AD6655 EVALUATION BOARD
The AD6655 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or optionally through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry. Each input configuration can be selected by proper connection of various components (see Figure 85 to Figure 94). Figure 84 shows the typical bench characterization setup used to evaluate the ac performance of the AD6655. It is critical that the signal sources used for the analog input and clock have very low phase noise (<<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. See Figure 85 to Figure 102 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. External supplies can be used to operate the evaluation board by removing L1, L3, L4, and L13 to disconnect the voltage regulators supplied from the switching power supply. This enables the user to individually bias each section of the board. Use P3 and P4 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for AVDD and DVDD; a separate 1.8 V to 3.3 V supply is recommended for DRVDD. To operate the evaluation board using the AD8352 option, a separate 5.0 V supply (AMP VDD) with a 1 A current capability is needed. To operate the evaluation board using the alternate SPI options, a separate 3.3 V analog supply (VS) is needed, in addition to the other supplies. The 3.3 V supply (VS) should have a 1 A current capability, as well. Solder Jumper SJ35 allows the user to separate AVDD and DVDD, if desired.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA100A signal generators or the equivalent. Use 1 m long, shielded, RG-58, 50 coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude for the ADC. The AD6655 evaluation board from Analog Devices, Inc., can accept a ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended that a multipole, narrow-band, band-pass filter with 50 terminations be used. Band-pass filters of this type are available from TTE, Allen Avionics, and K&L Microwave, Inc. Connect the filter directly to the evaluation board, if possible.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The output of the supply is a 2.1 mm inner diameter circular jack that connects to the PCB at J16. Once on the PC board, the 6 V supply is fused and conditioned before connection to six low dropout linear regulators that supply the proper bias to each of the various sections on the board.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog Devices standard ADC data capture board (HSC-ADC-EVALCZ). For more information on the ADC data capture boards and their optional settings, visit www.analog.com/FIFO.
WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX SWITCHING POWER SUPPLY ROHDE & SCHWARZ, SMA100A, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, SMA100A, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, SMA100A, 2V p-p SIGNAL SYNTHESIZER -
5.0V + -
1.8V +
3.3V - + -
3.3V + -
3.3V +
GND
GND
GND
GND
GND
VS
AMP VDD
AVDD IN
DRVDD IN
VCP
BAND-PASS FILTER
AINA
14-BIT PARALLEL CMOS 14-BIT PARALLEL CMOS SPI
HSC-ADC-EVALCZ FPGA BASED DATA CAPTURE BOARD
PC RUNNING VISUAL ANALOG AND SPI CONTROLLER SOFTWARE
BAND-PASS FILTER
AINB
AD6655
EVALUATION BOARD
USB CONNECTION SPI
06709-108
CLK
Figure 84. Evaluation Board Connection
Rev. 0 | Page 61 of 84
AD6655
DEFAULT OPERATION AND JUMPER SELECTION SETTINGS
The following is a list of the default and optional settings or modes allowed on the AD6655 evaluation board.
CSB
The CSB pin is internally pulled up, setting the chip into external pin mode, to ignore the SDIO and SCLK information. To connect the control of the CSB pin to the SPI circuitry on the evaluation board, connect J21, Pin 1 to J21, Pin 2.
POWER
Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the data format of the outputs. If the pin is left floating, the pin is internally pulled down, setting the default data format condition to offset binary. Connecting J2, Pin 1 to J2, Pin 2 sets the format to twos complement. If the SPI port is in serial pin mode, connecting J2, Pin 2 to J2, Pin 3 connects the SCLK pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section).
VIN
The evaluation board is set up for a double balun configuration analog input with optimum 50 impedance matching from 70 MHz to 200 MHz. For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed (see Table 14). The common mode of the analog inputs is developed from the center tap of the transformer via the CML pin of the ADC (see the Analog Input Considerations section).
VREF
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin sets the duty cycle stabilizer. If the pin is left floating, the pin is internally pulled up, setting the default condition to DCS enabled. To disable the DCS, connect J1, Pin 1 to J1, Pin 2. If the SPI port is in serial pin mode, connecting J1, Pin 2 to J1, Pin 3 connects the SDIO pin to the on-board SPI circuitry (see the Serial Port Interface (SPI) section).
VREF is set to 1.0 V by tying the SENSE pin to ground by adding a jumper on Header J5 (Pin 1 to Pin 2). This causes the ADC to operate in 2.0 V p-p full-scale range. To place the ADC in 1.0 V p-p mode (VREF = 0.5 V), a jumper should be placed on Header J4. A separate external reference option is also included on the evaluation board. To use an external reference, connect J6 (Pin 1 to Pin 2) and provide an external reference at TP5. Proper use of the VREF options is detailed in the Voltage Reference section.
RBIAS
ALTERNATIVE CLOCK CONFIGURATIONS
Two alternate clocking options are provided on the AD6655 evaluation board. The first option is to use an on-board crystal oscillator (Y1) to provide the clock input to the part. To enable this crystal, Resistor R8 (0 ) and Resistor R85 (10 k) should be installed, and Resistor R82 and Resistor R30 should be removed. A second clock option is to use a differential LVPECL clock to drive the ADC input using the AD9516 (U2). When using this drive option, the AD9516 charge pump filter components need to be populated (see Figure 89). Consult the AD9516 data sheet for more information. To configure the clock input from S5 to drive the AD9516 reference input instead of directly driving the ADC, the following components need to be added, removed, and/or changed. 1. 2. Remove R32, R33, R99, and R101 in the default clock path. Populate C78 and C79 with 0.001 F capacitors and R78 and R79 with 0 resistors in the clock path.
RBIAS requires a 10 k resistor (R503) to ground and is used to set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple baluncoupled circuit using a high bandwidth 1:1 impedance ratio balun (T5) that adds a very low amount of jitter to the clock path. The clock input is 50 terminated and ac-coupled to handle singleended sine wave inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. When the AD6655 input clock divider is utilized, clock frequencies up to 625 MHz can be input into the evaluation board through Connector S5.
PDWN
To enable the power-down feature, connect J7, shorting the PDWN pin to AVDD.
In addition, unused AD9516 outputs (one LVDS and one LVPECL) are routed to optional Connector S8 through Connector S11 on the evaluation board.
Rev. 0 | Page 62 of 84
AD6655
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION
This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet. To configure the analog input to drive the AD8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for Channel A. For Channel B, the corresponding components should be changed. 1. 2. Remove C1, C17, C18, and C117 in the default analog input path. Populate C8 and C9 with 0.1 F capacitors in the analog input path. To drive the AD8352 in the differential input mode, populate the T10 transformer; the R1, R37, R39, R126, and R127 resistors; and the C10, C11, and C125 capacitors. Populate the optional amplifier output path with the desired components including an optional low-pass filter. Install 0 resistors, R44 and R48. R43 and R47 should be increased (typically to 100 ) to increase to 200 the output impedance seen by the AD8352.
3.
Rev. 0 | Page 63 of 84
AD6655
SCHEMATICS
R40 AMPVD D
10K OHM
R41
AB
10K OHM
OPTIONAL AMPLIFIER INPUT PATH
C2 0.1U
W1
C8 R31 AMPVD D 0.1U R38 14 VCM GND 11 RGP Z1 3 RGN 10 9 C16 L15 1 IND060 3 0.001 U 2
120NH DNP 0 OHM 0 OHM
C10 R37
INA0.1U 16 VIP 1 RDP 2 0.001 U L14 1 IND060 3 12 C12 2
120NH
R29
15 ENB
13 VCC
ETC1-1-1 3
24.9 OHM
2
AMPA
R126
R36
C12 5 .3P F VON AD835 2 GND GND 5 6 7 8 VCC 4 RDN VIN
INA+ 0.1U
24.9 OHM
4 3 T10 R54
0 OHM
100 OHM
C9
P S
R12 7
2
DNP
4.12K
5 VOP
1
DNP
L16 1 IND060 180NH 3 DNP C4 18P F DNP L17 1 IND060 3 DNP
180NH
C13 9 12P F DNP 2 AMP+ A DNP
F
R35
C11 R39
0 OHM
AMPVD D 0.1U C22 0.1U C23 0.1U C27 10U
TP14 1
INA-
DEFAULT AMPLIFIER INPUT PATH
R49 AVD D R11 0 CML
0 OHM 0 OHM
2
R28
R43
57.6 OHM
6 1ADT1_1WT T2
F
33 OHM
F
0 OHM P S
AIN+
ETC1-1-13
1 0.1U 0.1U
0 OHM
33 OHM
C1
R47
2
R1
57.6 OHM
R4
INA +
0 OHM
06709-200
Figure 85. Evaluation Board Schematic, Channel A Analog Inputs
R44 AMPA C17 4 5 0.1U
33 OHM
S2 5 1
ETC1-1-13
2 1 C18 5
C3 0.1U
RES040 2
57.6 OHM
4
3 2
S
P
0 OHM
R5
Rev. 0 | Page 64 of 84
C11 7 T7 C47 0.1U 2 0.1U T1 3 4 CML 3 R26 R2 R42 R27 R48 AMP+ A
0 OHM 33 OHM
0 OHM
S1
AIN-
1
0 OHM
R12 0
VIN-A
TP15 1 R50 C5 4.7P F AVD D
0 OHM
VIN+ A
R12 1
Transformer/amp channel A
R131 AMPVD D
10K OH M
W2
OPTIONAL AMPLIFIER INPUT PATH
R53
C30 R66
0 OH M 0 OH M
C38 R132
0.1U R133
DN P
0.1U
16 VIP ENB VCM GND 11 RGP Z2 3 RGN VON 10 9 C140 L19 1 IND060 3 0.001 U
120NH
15 VCC 12 L18 1 IND060 3 0.001 U
120NH
14 C46
13 2 DNP 2
180NH
R134
24.9 OH M
1 RDP
AMPVDD
INB+
10K OH M
AB C24 0.1U
L20 1 IND060 3 DNP
AMP+B
R68
DN P
ETC1-1-1 3
2 C128 VOP
5
1
R128
4.12K
R129
C31 4
F
2 .3PF AD835 2 4 RDN GND GND 5 6 7 8 VCC VIN T11 3
100 OH M
P
S
C19 18P F DNP 2 DNP 2
180NH
C29 12P F DNP
INB0.1U
R135
24.9 OH M
R55
0 OH M
L21 1 IND060 3 DNP
AMP-B
C39 R6
0 OH M
AMPVD D TP16 1 C60 0.1U C61 0.1U C62 10U
0.1U
DEFAULT AMP LIFIER INPUT PATH
INB -
R80 AVDD
0 OH M
R111 CML
0 OH M 0 OH M
R94 AMP-B C7
2
R51
R70
57.6 OH M
T8 5
P S
R67
57.6 OH M 0 OH M
33 OH M
S3 5 C6 2
F P S
2 1 4
F
CML
0 OH M
4 3 0.1U T3
33 OH M
AIN+
INB+
2
R52
57.6 OH M
R69
0 OH M
06709-201
Figure 86. Evaluation Board Schematic, Channel B Analog Inputs
R71
1
R123
T4
3 C82
C83 0.1U VIN+B
0 OH M
RES0402
0.1U
R72
Rev. 0 | Page 65 of 84
C28
ADT1_1W T
S4
1 0.1U 2 5 4
ETC1-1-1 3
R122 C51 0.1U 0.1U 3
ETC1-1-1 3
R73
33 OH M
0 OH M
1 6
TP17 1
VIN- B
AIN1
RES040 2
R81 AVDD R96 C84 4.7P F
0 OH M
R74 R95 AMP+B
0 OH M 33 OH M
AD6655
AD6655
VS
R85
10KOHM
C145
0.1U
R82
10KOHM
R78 ALTCLK+ 0 OHM C20 C64 OPT_CLK+ C78 OPT_CLK+ 0.001U 3 S5 SMA200U P 2 1 1 ADT1_1W T 0.001U 5 P 4 1 S2 3 0 OHM R90 6 T9 C63 5 R32 0 OHM 0 OHM 0.1U 4 R99 0.1U CLK +
R8
2
0 OHM
0.001U
C56
R30
57.6OHM
R33
0 OHM
OPT_CLK0.001U 0.001U
2
1 R34 R7 57.6OHM
ENC\
DNP
C77 OPT_CLK0.001U R101 0 OHM R79 ALTCLK0 OHM R84
06709-202
CLK 0.1U
Figure 87. Evaluation Board Schematic, DUT Clock Input
24.9OHM C21
2
TP2
Rev. 0 | Page 66 of 84
F
0 OHM T5 ETC1-1-1 3
SMA200U P
S6 1 R3 C94
C79
24.9OHM R83
ENC
OUT6 P
R11
5.1K
R12
4.12K
OUT6 N C14 1 VS_OUT_D R
VS
OPT_CLK -
SYN C 0.001 U VS S8 C88 1 0.1U
AGN D VS
OPT_CLK +
R9
OUT 56 0
REFI 64 N
OUT0 55 B
OUT 53 1
REFIN 63 B
CP_RSE62 T
VS_PLL_61 2
GND_REF 59
VS_RE 57 F
OUT1 52 B
100 OHM
2
VS_OUT67_ 250
RSET_CLOC K58
VS_PRESCALE R60
VS_OUT01_DR V54
VS_OUT01_DI51 V
VS_OUT67_ 149
R75
100 OHM
LVDS
TP8 1 S9 C87 1 0.1U
OUTPUT
VS REFMO N
2
1
VS_PLL_ 1 OUT6 B OUT 7 OUT7 B GND_ES D OUT 2 OUT2 B AD9516_64LFCS P U2
42 43 44 45 46 47
OUT 6
48
TP20
3
LD LD
0 OHM
R10
TP19 TES T 1 REFMO N VCP
5 4
TEST
1 VCP CP
2
C10 4 0.1U STATU S
6
AGN D
LVPECL TO ADC
ALTCLK ALTCLK + VS_OUT_D R S10 C85
STATU S
CP TP18 TES T 1 REF_SE L
7
REF_SE L
SYNC B LF BYPASS_LD O
10 9
8
SYNC B
VS_OUT23_DR 41 V OUT 3 OUT3 B VS_OUT23_DI V
40
AD9516
BYPASS_LD O VS
12 11
LF
R86 200
39
1 R88 200
38
CLK IN
VS_VC O C80 18P F VS_CLK_DIS T
13
VCXO_CLK +
0.1U
2
VS GND_OUT89_DI 37 V OUT9 B OUT 9 OUT8 B OUT 8
36
2
R89
49.9 OHM
CSB
NC2
NC3
NC4
SDO
SDIO
RESET B
PDB
OUT 4
OUT4 B
VS_OUT45_DR V
OUT 5
OUT5 B
VS_OUT45_DI V
VS_OUT89_ 1
21
17
18
19
20
22
23
24
25
26
27
28
29
30
31
VCXO_CLK -
SDO
VS_OUT_D R
RESET B
VS_OUT_D R
C96 0.1U C97 0.1U
CSB_ 2
C10 0 0.1U C10 1 0.1U C98 0.1U C99 0.1U
SDI
PDB
VCP
32
VS_OUT89_ 2
06709-203
Figure 88. Evaluation Board Schematic, Optional AD9516 Clock Circuit
AGN D
PAD
Rev. 0 | Page 67 of 84
CLK C14 2
15 14
S7
1 CLK B
R12 4
35
0 OHM
S11
34
LVPECL OUTPUT
C86
33
RES040 2
NC1
0.1U SCLK SCLK C14 3
16
1 0.1U
2
R91 200 0.1U R92 200
R12 5
0 OHM
RES040 2
VS
AD6655
AD6655
VS
R76 200
VS
A C
C26 0.1U
U3 LD Y1 VCC Y2
33 OH M 0 OH M
SMA200UP
S12 C25 3 A2 4 SYNC 0.1U R46 R104 GND
A1
TP1
1 6
SYNC
R100
10K OH M
NL27WZ04 RES0402 RES0402 RES0402
1
2
1
2 5
VS
VS
VS
VS
R102
R103
10K OH M
10K OH M
R105
RES0402 RES0402
10K OH M
REF_SE L PD B SYNC B
R45
57.6 OH M
RES0603
RES0402 RESET B
R87
24.9 OH M
VCP
R116
R106
10K OH M
RES0402
R108
10K OH M
R109
RES0402
10K OH M
06709-204
Figure 89. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input
R137 1 FREQ_CTRL_V VAL
0 OH M
R98 VAL C144 SEL
BYPASS_LDO
RES0402
Rev. 0 | Page 68 of 84
R97 6 VCC VAL C91
RES0402
R136
R117 VCP R114 2 OUT_DISABLE 5 OUT1
0 OH M
RES0402
CP C92 SEL
VAL
C90 SEL R93 VAL SEL 3 GND C89 SEL U25 VS-500 4 OUT2
RES0402
RES0402
10K OH M
0 OH M
R107
Charge Pump Filter
OSCVECTRON_VS500
LF
VCXO_CLK+ R139 VCXO_CLK0 OH M
RES0402
PWR_SDFS
R113 DRVDD R115 0 OHM TP3
RES0402
PWR_SCL K PWR_SDO FD3 A FD2 A FD1 A FD0 A
1 0 OHM
8 7 6 5 4 3 2 1
RES040 2
R112
0 OHM
9 10 11 12 13 14 15 16
R62 DRVD D C36 0.1U
22ohm
RPAK8
J7 - INSTALLFORPDWN J8 - INSTALLFOROUTPUTDISABL E
RES0402
22ohm
C35
DVDD
0.001U
9 10 11 12 13 14 15 16
RPAK8
8 7 6 5 4 3 2 1 R61
D13 A D12 A D11 A D10 A D9A D8A D7A D6A
32
31
30
29
28
27
26
25
24
23 D9A
22 D8A
21
20
19 D7A
18 D6A
17 D5A
D4A D3A D2A D1A DOA_LSB_ DCOA DCOB 22ohm 16 15 14 13 12 11 10
RPAK8
1
DRVDD1 DRGND1
D10A
D12A
D11A
FD3A
FD2A
FD1A
FD0A
DVDD1
33 34 35 AVDD 36 37 38 39 VREF SENSE CML RBIAS VIN-B VIN+B AVDD2 AVDD3 46 47 48 SPI_SDIO/DCS VIN-A VIN+A VIN+ A AVDD1 PWR_SDFS PWR_SCLK_PDWN
D13A_MSB_
J4 - INSTALLFOR 0.5V VREF/IV INPUTSPAN J5 - INSTALLFORIV VREF/2VINPUTSPAN J6 - INSTALLFOR EXTERNALREFERENCEMODE
PWR_SDO/OEB
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1 R60
D5A D4A D3A D2A D1A D0A DCO A DCO B
C15 1U VIN-A
C14 0.1U
1 CM L 41 0.1U 42 VIN-B 43 44 45 VIN+ B AVDD AVDD SPI_SDI O SPI_SCL K AVDD 10KOHM
RES0402
C32
40
AD6655
D13B_MSB_ D12B D11B D10B D9B D8B D7B D6B
9 22ohm 8 7 6 5 4 3 2 9 10 11 12 13 14 15 16
RPAK8
1 1
8 7 6 5 4 3 2 1 R59 D13 B D12 B D11 B D10 B D9B D8B D7B D6B
CLK +
CLK -
SYNC
SPI_CSB
DVDD
06709-205
22ohm
Figure 90. Evaluation Board Schematic, DUT
TP5
Rev. 0 | Page 69 of 84
RES0402 R63 0 OHM
TP6 R64
1
1
SPI_CSB DRGND FD0B FD1B FD2B FD3B DVDD2 SYNC CLK+
SPI_SCLK/DFS U1 DRVDD C33
D0B_LSB_
CLK49 50
D1B
D2B
D3B
D4B
D5B
1
0.001U
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C34 DRVD D 0.1U 22ohm R58 5 6 7 8
RPAK4
DVDD C127 0.001U C126 0.001U C40 0.1U C120 0.1U
4 3 2 1
D5B D4B D3B D2B
AVDD C122 0.001U C109 0.1U C121 0.1U C137 0.001U
9 10 11 12 13 14 15 16
RPAK8
8 7 6 5 4 3 2 1 R57
D1B D0B FD3 B FD2 B FD1 B FD0 B
AD6655
AD6655
DIGITAL/HSC-ADC-EVALCZ INTERFACE
CHANNELA
SDFS_OUT SCLK_OUT SDO_OU T V_DI G VS V_DIG
U15
PWR_SDFS PWR_SCLK
PWR_SDO
V_DI G
FD3 A FD2 A FD1 A FD0 A
R118 10KOHM
C65 0.1U
RES040 2
C66 0.1U
C67 0.1U
C68 0.1U
C69 0.1U
C70 0.1U
C71 0.1U
D13 A D12 A V_DI G D11 A D10 A
TYCO_ HM-ZD
J12
TP21 TEST 1 RESETB 0 OHM
RES0402
D9A D8A R119
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
74VCX162244MT D VS SDO R143 0 OHM
RES0402
U16
BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 V_DIG C72 0.1U R142 SDI
RES040 2
R140
10KOHM
D7A D6A
V_DIG CSB_2 J10 SCLK
RES0402 RES0402
D5A D4A V_DI G D3A D2A R141 0 OHM R144 SDFS_OU T SCLK_OU T 0 OHM
RES0402
B1 C10 D10 C9 D9 A9 B9 C8 D8 A8 B8 C7 D7 A7 B7 C6 D6 A6 B6 A10 B10 C5 D5 A5 B5 C4 D4 A4 B4 C3 D3 A3 B3 C2 D2 A2 B2 C1 D1 A1 0 OHM C73 0.1U C74 0.1U C75 0.1U
C76 0.1U
D1A D0A DCO A DCO B
TYCO_HM-ZD
R130 VAL
OUT6N CSB 0 OHM
RES0402
R145 SYNC TP23 TEST 1 TP24 TEST 1
R77
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 V_DI G V_DI G OUT6P J11
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
B1 C10 D10 C9 D9 A9 B9 C8 D8 A8 B8 C7 D7 A7 B7 C6 D6 A6 B6 A10 B10 C5 D5 A5 B5 C4 D4 A4 B4 C3 D3 A3 B3 C2 D2 A2 B2 C1 D1 A1 TP22 TEST 1 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 OUT6P
100OHM
06709-206
Figure 91. Evaluation Board Schematic, Digital Output Interface
DG10 DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1 BG10 BG9 BG8 BG7 BG6 BG5 BG4 BG3 BG2 BG1
Rev. 0 | Page 70 of 84
SDO_OU T OUT6N
D13 B D12 B V_DI G D11 B D10 B
D9B D8B
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
74VCX162244MT D
U17
D7B D6B
A1 D1 C1 B2 A2 D2 C2 B3 A3 D3 C3 B4 A4 D4 C4 B5 A5 D5 C5 B10 A10 B6 A6 D6 C6 B7 A7 D7 C7 B8 A8 D8 C8 B9 A9 D9 C9 D10 C10 B1
D5B D4B V_DI G D3B D2B
D1B D0B FD3 B FD2 B
FD1 B FD0 B V_DI G
74VCX162244MT D
TYCO_HM-ZD CHANNELB
R19 R20 V_DIG U7 1KOHM 1KOHM 6 5 V_DIG R21 VS 1KOHM SDO C13 0.1U J1 3 CSB_2 R22 V_DI G R24 C81 0.1U
RES0603 RES0603 RES0603 RES0603
SDI R18 1 A1 GND A2
NC7WZ07P6 X
Y1 VCC Y2 4
10KOHM
RES0402
2 3
V_DI G
1
CSB
SCLK 100KOHM 3 J2 1
SDI
SPI_SDI O
J1 - JUMPERPINS 2 TO 3 FOR SPI OPERATIO N JUMPERPINS 1 TO 2 FOR DCS ENABL E J2 - JUMPERPINS 2 TO 3 FOR SPI OPERATIO N JUMPERPINS 1 TO 2 FOR TWOS COMPLIMENT OUTPUT J21 - INSTALLJUMPERFOR SPI OPERATIO N
SDO 10KOHM
RES0402
R65
10KOHM
RES040 2
06709-207
Figure 92. Evaluation Board Schematic, SPI Circuitry
U8 6 5 V_DI G 4 R17 V_DI G 100KOHM
RES0603
Rev. 0 | Page 71 of 84
SCLK 2 GND A2
NC7WZ16P6 X
V_DI G
1 A1 VCC Y2
RES0603
R23 SPI_SCL K 100KOHM
Y1
CSB
3
SPI_CS B
AD6655
AD6655
POWER INPU T 6V, 2A MAX
F1 CR8 SHOT_RECT
F2 S2A_REC T S2A_REC T S2A_REC T
J16 1
PWR_I N
2 CR10 CR11 VR3 3 IN PAD OUT
ADP3339 IND1210
1 1 CR12 2
2
1 3 1 BIAS CB 2 CG 4
2
1
2
2
POWER_JACK
CR7
SMDC110 F C41 10U CG5 3 PSG 1 L3 2
AVDDI N 10u h
1
A C
BNX-01 6
R16
261 OH M
C42 1U
1
GND
RES0603
AVDDI N
S2A_REC T
CG6
4
C43 1U
ADP3334 8 IN 7 IN2
C44 1U
10U H
VR1
10u h
OPTIONAL POWER SUPPLY INPUT S
1 C45 1U
IND1210
2
DRVDDI N
R13
P3 P11
GND
SJ35
1
IND1210
P22
2
AVD D
P33
L6 C52 10U C57 0.1U
SD 6
5
R14
P55
10U H
P66
1
IND1210
2 DVDD
TP25 1
06709-208
Figure 93. Evaluation Board Schematic, Power Supply
OUT 1 OUT2 2 FB 3
L9 C102 10U C103 0.1U
L4
Rev. 0 | Page 72 of 84
1
IND1210
P4
2
DRVD D
DRVDD SETTIN G DRVD D R1 3
V_DI G
DRVDDI N
P1
10u h
IND1210
L10 1
10u h
147K OH M
P44
76.8 KOH M
C93 0.001U
L11 2
R1 4 GND TEST POINT S
T 1 P4 TP9 1 TP10 1 TP12 1 TP13 1
P2
C54 10U C59 0.1U
VS
C53 10U
C58 0.1U
3.3 2.5 1.8
140 K 107 K 76.8 K
78.7 K 94.0 K 147 K
P3
P4
VCP
1 1
VR5 PWR_IN 3 IN
ADP3339
4
PAD OUT L12
IND1210
1 VS_OUT_DR
10u h 2
C133 1U
1
GND
C134 1U
VR4 PWR_IN 3 IN
ADP333 9
4
4
1
GND
SJ36
10U H OUT C130 1U 1
IND1210
PAD
2 L1
AMPVDD
VR6 10u h OUT L13 C136 1U 1
IND1210
PWR_IN
3 IN
ADP3339
PAD VS
2
C129 1U
C135 1U
1
GND
SJ37
VS
ADP3334
PWR_IN 1
IND1210
VR2
10U H 2 VCP L8
C110 0.1U
C112 0.1U
C108 0.1U
C111 0.1U
C115 0.1U
C114 0.1U
C113 0.1U
C107 0.1U
C116 0.1U
C105 0.1U
8 IN 7 IN2
R25 140KOH M
C132 1U C95
OUT 1 OUT2 2 FB 3
C131 1U
GND
R15
VS_OUT_D R VCP VCP VS
06709-209
Figure 94. Evaluation Board Schematic, Power Supply (Continued)
0.001U
C119 10U
C124 10U
Power Supply ByPass Capaci tors
78.7KOH M
C118 10U
Rev. 0 | Page 73 of 84
SD 6 5
AD6655
AD6655
EVALUATION BOARD LAYOUTS
Figure 95. Evaluation Board Layout, Primary Side
Rev. 0 | Page 74 of 84
06709-100
AD6655
Figure 96. Evaluation Board Layout, Ground Plane
Rev. 0 | Page 75 of 84
06709-101
AD6655
Figure 97. Evaluation Board Layout, Power Plane
Rev. 0 | Page 76 of 84
06709-102
AD6655
Figure 98. Evaluation Board Layout, Power Plane
Rev. 0 | Page 77 of 84
06709-103
AD6655
Figure 99. Evaluation Board Layout, Ground Plane
Rev. 0 | Page 78 of 84
06709-104
AD6655
Figure 100. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. 0 | Page 79 of 84
06709-105
AD6655
Figure 101. Evaluation Board Layout, Silkscreen, Primary Side
Rev. 0 | Page 80 of 84
06709-106
AD6655
Figure 102. Evaluation Board Layout, Silkscreen, Secondary Side
Rev. 0 | Page 81 of 84
06709-107
AD6655
BILL OF MATERIALS
Table 30. Evaluation Board Bill of Materials (BOM) 1, 2
Item 1 2 Qty 1 55 Reference Designator AD6655CE_REVB C1 to C3, C6, C7, C13, C14, C17, C18, C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, C108, C110 to C116, C145 C80 C5, C84 C33, C35, C63, C93 to C95, C122, C126, C127, C137 C15, C42 to C45, C129 to C136 C27, C41, C52 to C54, C62, C102, C118, C119, C124 CR5 CR6, CR9 Description PCB 0.1 F, 16 V ceramic capacitor, SMT 0402 Package PCB C0402SM Manufacturer Analog Devices Murata Mfg. Part Number GRM155R71C104KA88D
3 4 5
1 2 10
18 pF, COG, 50 V, 5% ceramic capacitor, SMT 0402 4.7 pF, COG, 50 V, 5% ceramic capacitor, SMT 0402 0.001 F, X7R, 25 V, 10% ceramic capacitor, SMT 0402 1 F, X5R, 25 V, 10% ceramic capacitor, SMT 0805 10 F, X5R, 10 V, 10% ceramic capacitor, SMT 1206 Schottky diode HSMS2822, SOT23 LED RED, SMT, 0603, SS-type
C0402SM C0402SM C0402SM
Murata Murata Murata
GJM1555C1H180JB01J GJM1555C1H4R7CB01J GRM155R71H102KA01D
6 7
13 10
C0805 C1206
Murata Murata
GR4M219R61A105KC01D GRM31CR61C106KC31L
8 9
1 2
SOT23 LED0603
Avago Technologies Panasonic
HSMS-2822-BLKG LNJ208R8ARA
10 11 12 13 14 15 16 17 18 19 20 21 22 23
4 1 1 1 2 9 3 1 1 10 1 1 3 27
CR7, CR10 to CR12 CR8 F1 F2 J1, J2 J4 to J9, J18, J19, J21 J10 to J12 J14 J16 L1, L3, L4, L6, L8 to L13 P3 P4 R7, R30, R45 R2, R3, R4, R32, R33, R42, R64, R67, R69, R90, R96, R99, R101, R104, R110 to F113, R115, R119, R121, R123, R141 to R145 R13 R25 R14 R15
50 V, 2 A diode 30 V, 3 A diode EMI filter 6.0 V, 3.0 A, trip current resettable fuse 3-pin, male, single row, straight header 2-pin, male, straight header Interface connector 8-pin, male, double row, straight header DC power jack connector 10 H, 2 A bead core, 1210 6-terminal connector 4-terminal connector 57.6 , 0603, 1/10 W, 1% resistor 0 , 1/16 W, 5% resistor
DO_214AA DO_214AB FLTHMURATABNX01 L1206 HDR3 HDR2 TYCO_HM_ZD CNBERG2X4H350LD PWR_JACK1 1210 PTMICRO6 PTMICRO4 R0603 R0402SM
Micro Commercial Components Micro Commercial Components Murata Tyco Raychem Samtec Samtec Tyco Samtec Cui Stack Panasonic Weiland Electric, Inc. Weiland Electric, Inc. NIC Components NIC Components
S2A-TP SK33-TP BNX016-01 NANOSMDC150F-2 TWS-1003-08-G-S TWS-102-08-G-S 6469169-1 TSW-104-08-T-D PJ-002A EXC-CL3225U1 Z5.531.3625.0 Z5.531.3425.0 NRC06F57R6TRF NRC04ZOTRF
24 25 26 27
1 1 1 1
76.8 k, 0603, 1/10 W, 1% resistor 140 k, 0603, 1/10 W, 1% resistor 147 k, 0603, 1/10 W, 1% resistor 78.7 k, 0603, 1/10 W, 1% resistor
R0603 R0603 R0603 R0603
NIC Components NIC Components NIC Components NIC Components
NRC06F7682TRF NRC06F1403TRF NRC06F1473TRF NRC06F7872TRF
Rev. 0 | Page 82 of 84
AD6655
Item 28 29 30 31 32 Qty 1 3 7 3 9 Reference Designator R16 R17, R22, R23 R18, R24, R63, R65, R82, R118, R140 R19, R21 R26, R27, R43, R46, R47, R70, R71, R73, R74 R57, R59 to R62 R58 R76 S2, S3, S5, S12 SJ35 T1 to T5 U1 U2 U3 U7 U8 U15 to U17 VR1, VR2 VR3 VR4 VR5, VR6 Y1 Z1, Z2 Description 261 , 0603, 1/10 W, 1% resistor 100 k, 0603, 1/10 W, 1% resistor 10 k, 0402, 1/16 W, 1% resistor 1 k, 0603, 1/10 W, 1% resistor 33 , 0402, 1/16 W, 5% resistor Package R0603 R0603 R0402SM R0603 R0402SM Manufacturer NIC Components NIC Components NIC Components NIC Components NIC Components Mfg. Part Number NRC06F2610TRF NRC06F1003TRF NRC04F1002TRF NRC06F1001TRF NRC04J330TRF
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2
5 1 1 4 1 5 1 1 1 1 1 3 2 1 1 2 1 2
22 , 16-pin, 8-resistor, resistor array 22 , 8-pin, 4-resistor, resistor array 200 , 0402, 1/16 W, 1% resistor SMA, inline, male, coaxial connector 0 , 1/8 W, 1% resistor Balun IC, AD6655 Clock distribution, PLL IC Dual inverter IC Dual buffer IC, open-drain circuits UHS dual buffer IC 16-bit CMOS buffer IC Adjustable regulator 1.8 V high accuracy regulator 5.0 V high accuracy regulator 3.3 V high accuracy regulator Oscillator clock, VFAC3 High speed IC, op amp
R_742 RES_ARRY R0402SM SMA_EDGE SLDR_PAD2MUYLAR TRAN6B LFCSP64-9X9-9E LFCSP64-9X9 SC70_6 SC70_6 SC70_6 TSOP48_8_1MM LFCSP8-3X3 SOT223-HS SOT223-HS SOT223-HS OSC-CTS-CB3 LFCSP16-3X3-PAD
CTS Corporation CTS Corporation NIC Components Emerson Network Power NIC Components M/A-COM Analog Devices Analog Devices Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Analog Devices Analog Devices Analog Devices Analog Devices Valpey Fisher Analog Devices
742C163220JPTR 742C083220JPTR NCR04F2000TRF 142-0701-201 NRC10ZOTRF MABA-007159-000000 AD6655BCPZ AD9516-4BCPZ NC7WZ04P6X_NL NC7WZ07P6X_NL NC7WZ16P6X_NL 74VCX16244MTDX_NL ADP3334ACPZ ADP3339AKCZ-1.8 ADP3339AKCZ-5.0 ADP3339AKCZ-3.3 VFAC3-BHL AD8352ACPZ
This bill of materials is RoHS compliant. The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.
Rev. 0 | Page 83 of 84
AD6655 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48 PIN 1 INDICATOR 64 1
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
7.25 7.10 SQ 6.95
0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
33 32
16 17
7.50 REF
0.25 MIN
1.00 0.85 0.80
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 103. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD6655BCPZ-150 1 AD6655BCPZ-1251 AD6655BCPZ-1051 AD6655BCPZ-801 AD6655-125EBZ1 AD6655-150EBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD6655 and Software Evaluation Board with AD6655 and Software
Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06709-0-11/07(0)
Rev. 0 | Page 84 of 84
051007-C
Package Option CP-64-3 CP-64-3 CP-64-3 CP-64-3

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